Types pf flip flops with Verilog code

Flip flop are basic storage elements and the soul for sequential circuit design. Based on the application & the need we can design and use a flip flop. Few of the flip flops which are usually used for sequential circuits and for memory design are

You can code for any given FF with the truth table and thereby converting them into a logic gate configuration which is quite a simple task as far as these flip flops are concerned.

• SR FF
• JK FF
• D FF
• T- FF

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SR-FF

     Characteristic equation: Q(next) = S + R'Q ,SR = 0

S	R	Q(next)
0	0	Q
0	1	0
1	0	1
1	1	undefined

From the truth table its clear that the FF has two inputs. S & R represents Set & Reset respectively. To model this FF we can use the CASE statement and define all the four input combination and the related output .Its always a good design to have a reset for your FF so as to bring it to a defined stage at any point of time asynchronously. If your design requires the use of output and its compliment then it can also be defined in your code as follows:

Verilog code for SR Flip-Flop

module srff(s,r,clk,rst, q,qb);

    input s,r,clk,rst;

    output q,qb;

               reg q,qb; 

              reg [1:0]sr;

             always@(posedge clk,posedge rst)

            begin

             sr={s,r}; //concatenate S&R to a 2 bit value

             if(rst==0) // when reset is not asserted

                        begin

                        case (sr)

                        2'd1:q=1'b0;

                        2'd2:q=1'b1;

                        2'd3:q=1'b1;

                        default: begin end

                        endcase

                        end

            else                              // when reset is asserted 

            begin

                        q=1'b0;

                        end

                       

                        qb=~q;

                        end

 endmodule

 In the above design you must have noticed that the input combination "11" is also defined which is not true in case of SR FF as its a undetermined state. To correct the design u can model the same using gate level coding using NAND or NOR gates as shown using the inbuilt function   nand(); available in the library.

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J-K FF

     Q(next) = JQ' + K'Q

J	K	Q(next)
0	0	Q
0	1	0
1	0	1
1	1	Q'(toggle)

 This one is similar to the SR FF except that the "11" state defines a state where the output toggles between 1 & 0.  The same design for SR can be extended with two more nand gates to define the JK.

Verilog code for JK Flip Flop

`define TICK #2 //Flip-flop time delay 2 units

module jkflop(j,k,clk,rst,q);

input j,k,clk,rst;

output q;

reg q;

always @(posedge clk)begin

if(j==1 & k==1 & rst==0)begin

q =`TICK ~q; //Toggles

end

else if(j==1 & k==0 & rst==0)begin

q = `TICK 1; //Set

end

else if(j==0 & k==1)begin

q = `TICK 0; //Cleared

end

end

always @(posedge rst)begin

q = 0; //The reset normally has negligible delay and hence ignored.

end

 endmodule

The above code defines the time delay also for the FF.

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Link for the coupons : Here

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D-FF

                            Q(next) = D 

D	Q(next)
0	0
1	1

This one is the simplest of all the FF and also easy to model . Though its the simplest one its the most used FF for designs.

Verilog Code for D-Flip Flop

// code for dff

module Dff(input d,input clk,output reg q);

  always @(posedge clk) // note: lines whithin the always block are executed sequententialy 

  begin

  q=d;

  end 

endmodule

// code ends

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T-FF

                              Q(next) = TQ' + T'Q

T	Q(next)
0	Q
1	Q'

 This one is the next simplest FF after D. Here the output is  retains the previous state when input is 0. And when the input is 1 the output toggles i.e for every rising edge of the clock when input is 1 the output toggles from its previous value.

Verilog code for T flip flop

module tff_sync_reset (

data  , // Data Input

clk   , // Clock Input

reset , // Reset input

q       // Q output

);

input data, clk, reset ;

output q;

reg q;

always @ ( posedge clk)

if (~reset) begin

  q <= 1'b0;

end else if (data) begin

  q <= !q;

end

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