Friday, 6 September 2013

FIR FILTER DESIGN USING VERILOG








     FIR filters are is widely used in different applications such as biomedical, communication and control due to its easily implementation, stability and best performance. Its simplicity makes it attractive for many applications where it is need to minimize computational requirements.


Filters play an important role for removal of unwanted signal or noise from original input signal by removing the selected frequencies from incoming signal. They became much popular due to the increase of the digital signal processing.

 Comparison between FIR and IIR Filters

The non recursive (FIR) and recursive (IIR) filters have different characteristics for numbers of applications. The non recursive filters are chosen due to its best performance of numerical operations, differentiation and integration. The table 2.1 below shows the comparison between FIR and IIR filters.


IIR
FIR
More Efficient

Less Efficient
Analog Equivalent

No Analog Equivalent

May Be Unstable

Always Stable
Non-Linear Phase Response

Linear Phase Response

No Efficiency Gained by Decimation
Decimation Increases Efficiency





VERILOG CODE FOR FIR FILTER
// main module FIR
module filterfir(clk,rst,x,dataout);
input [7:0]x;
input clk,rst;
output [9:0]dataout;
wire [7:0]d1,d2,d3;
wire [7:0]m1,m2,m3,m4,m5;
wire [7:0]d11,d12,d13,d14;
parameter h0=3'b101;
parameter h1=3'b100;
parameter h2=3'b011;
parameter h3=3'b010;
parameter h4=3'b001;
assign m1=x>>h0;
dff u2(clk,rst,x,d11);
assign m2=d11>>h1;
assign d1=m1+m2;
dff u4(clk,rst,d11,d12);
assign m3=d12>>h2;
assign d2=d1+m3;
dff u6(clk,rst,d12,d13);
assign m4=d13>>h3;
assign d3=d2+m4;
dff u8(clk,rst,d13,d14);
assign m5=d14>>h4;
assign dataout=d3+m5;
endmodule

module dff(clk,rst,d,q);// sub module d flipflop
input clk,rst;
input [7:0]d;
output [7:0]q;
reg [7:0]q;
always@(posedge clk)
begin
if(rst==1)
begin
q=0;
end
else
begin
q=d;
end
end

endmodule


Please Note : Our course is now listed for Udemy training by Industry and leading companies use our courses  :
Analog Design- Intuitive Approach
Rc Circuits Analysis With LT Spice
Basics of Mosfet - Simplified View
Please use these links or share with someone who might be interested.
Note : Author discounts are already applied to these links. 

62 comments:

  1. any tb file to simulate this?

    ReplyDelete
    Replies
    1. Its a simple TB. just set the clock first . Initially make reset high and then make it low . At the same instant when reset is low load X value

      Delete
    2. Could you write it down ? It is my first time I use verilog ;)

      Delete
    3. pls, it will help me a lot

      Delete
    4. `timescale 1ns / 1ps

      ////////////////////////////////////////////////////////////////////////////////
      // Company:
      // Engineer:
      //
      // Create Date: 22:07:00 01/29/2014
      // Design Name: filterfir
      // Module Name: D:/fft/floating_mul/tst.v
      // Project Name: floating_mul
      // Target Device:
      // Tool versions:
      // Description:
      //
      // Verilog Test Fixture created by ISE for module: filterfir
      //
      // Dependencies:
      //
      // Revision:
      // Revision 0.01 - File Created
      // Additional Comments:
      //
      ////////////////////////////////////////////////////////////////////////////////

      module tst;

      // Inputs
      reg clk;
      reg rst;
      reg [7:0] x;

      // Outputs
      wire [9:0] dataout;

      // Instantiate the Unit Under Test (UUT)
      filterfir uut (
      .clk(clk),
      .rst(rst),
      .x(x),
      .dataout(dataout)
      );

      initial begin
      // Initialize Inputs
      clk = 0;
      rst = 0;
      x = 0;
      #100;

      rst = 1;
      #100;

      rst = 0;
      x = 8'd5;
      #100;
      x = 8'd10;
      #100;
      x = 8'd12;
      #100;
      x = 8'd15;
      #100;
      x = 8'd16;
      #100;



      end
      always begin #50 clk=~clk; end
      endmodule

      Delete
    5. Hello sir, can u help to write xdc file or top module of the fir filter

      Delete
  2. Hello Sir. Thank you for writing the FIR Filter code as well as testbench. Why the dataout is 10 bit while the input data x is 8 bit only. and what about Impulse response of the system (h), how it will be determined and on which parametrs it willl depend??

    ReplyDelete
    Replies
    1. Hello. you can change the size of ur i/p as well as o/p. here i have considered 10 bit taking into considering the fact that the sum can me a maximum of 1024 or below. And here we have defined the "h" as predefined constants (weight). I suggest you to work on FIR filter design on matlab and compare the results with the xilinx .

      Delete
    2. sir, if we shift right means we are dividing the input with filter coefficients instead of multiplication. please explain me.

      Delete
  3. sir my mtech project is to implement low cost fir filter using faithfully truncated multiplier using verilog in FPGA KIT
    please can you give me sugestions for this project..

    Thanks regards
    harish

    ReplyDelete
    Replies
    1. Harsh, i am doing the project that you did in 2014. i need the steps to implement the design. can you help me...Deepu

      Delete
  4. how we can find out various specifications of FIR FILTER like band width,Pass Band Stop Band and how we can observe the frequency response in XILINX ISE tool pls help me....

    ReplyDelete
    Replies
    1. take a workspace from simulink model and attach the audio file to it...it will show the sampling freq of ur signal.further u can calculate pb,cutoff

      Delete
    2. type" fdtool" in matlab

      Delete
  5. Sir can u please explain how an FIR filter can be implemented using MAC unit which was developed using Vedic Mathematics.
    Thank you

    ReplyDelete
  6. do you know of any iir verilog source code that I can view. had a look at myHDL but couldn't seem to get those examples running

    ReplyDelete
  7. how to run this code........?? how to verify this as FIR filter.......??
    i'm using verilog for the 1st time so pls help me..........

    ReplyDelete
  8. can u explain how it works.... i'm new to verilog help me..

    ReplyDelete
  9. This comment has been removed by the author.

    ReplyDelete
  10. Why sre you right shifting 'x'. It is to be multiplied there right?

    ReplyDelete
  11. Sir can u please explain how an FIR filter can be implemented using MAC unit which was developed using Vedic Mathematics.
    Thank you

    ReplyDelete
  12. sir could you please send me COMPLETE CODE OF 32 BIT MAC UNIT WITH AREA/POWER/TIMING related codes

    ReplyDelete
  13. Thanks a lot for the FIR code . sir could you please provide the code for gaussian filter

    ReplyDelete
  14. Hii,Can anyone provide me the 2D FIR filter code in verilog to obtain LL,LH,HL,HH subbands.The input is an image of size 256x256

    ReplyDelete
  15. Hi
    Anyone help me that how do i design FIR filter using Verilog Code using my own multiplier architecture(module) as a lower level module.

    ReplyDelete
  16. Hi
    Sir I got a project of designing an adaptive fir filter
    can you help me in this writing a verilog code

    ReplyDelete
  17. Sir Please can you explain the code...

    ReplyDelete
  18. Do You have tre iir filter verilog code?

    ReplyDelete
  19. Do You have tre iir filter verilog code?

    ReplyDelete
  20. hii,can i get the verilog code for FIR FILTER using MAC UNIT ??

    ReplyDelete
  21. can anyone help me with the fir filter using verilog code.

    ReplyDelete
  22. how do we design fir filter usomg mac unit?

    ReplyDelete
  23. sir when I simulated this code, (only for input 8'd5), the output according to the design should be 8'd3..But it is not showing the output at the next clock positive edge..There is some finite delay before it is getting constant at 8'd3. Is it because if the delay of Dff, multiplier and adder ?

    ReplyDelete
  24. Sir can u write digital fir filter using window methods like rectangular, hamming and Blackman for bandpass

    ReplyDelete
  25. Sir,
    I am working on FIR Filter Design using VERILOG, so plz help me on it. i dont know how the above codes i have to use??????

    ReplyDelete
  26. wat will be the output of a digital fir filter how can we justify that the output is perfect filter output

    ReplyDelete
  27. Why you used d-flip flop

    ReplyDelete
  28. hi sir i need to write 10 tap fir filter...how to change this code?

    ReplyDelete
  29. hi sir, i want to write code for 60 tap fir filter. for that i need to declare 60 parameters and 60 d flipflops.Is there any simple code for implementing fir like using a for loop? and want to declare coeffs in an array instead of writing 60 times?

    ReplyDelete
  30. Hi, you have the input of 8 bit length but a FF can pass only one bit at a time.Dont we have to use a serial shift register instead of a simple D-flip flop

    ReplyDelete
  31. hi,can you explain the basic convolution operation using this with an example.

    ReplyDelete
    Replies
    1. i will write it in a separate article soon

      Delete
  32. sir i have to make a project on a fir filter that removes noise from an incomming sound using verilog.I have some idea of verilog but i have no idea of fir filters.Can you please help me with this sir.also this project is based on 16 bits and should be for both signed and unsigned inputs.

    ReplyDelete
  33. Can you please give me a diagram to understand the code?

    ReplyDelete
  34. Sir, can you please provide block diagram for this code

    ReplyDelete
  35. Hi, this code is not supporting decimal numbers or fractions. what we have to do if our co-efficient are in fractions and input in decimal.
    Thanks

    ReplyDelete
  36. Sir, Could you help me? , I want to write the verilog code for 24tap adaptive LMS filter for noise cancellation...

    ReplyDelete
  37. Sir can you provide verilog code for IIR

    ReplyDelete
  38. hello sir. im looking for fir filter and find your code. and i did make time domain fir filter. but i want know about general fir filter's input signal. example sinewave have noise, and that signal pass the filter and erase the noise.

    is there have general input signal for fir filter? and how can i get exact coefficient for each filter in time domain

    ReplyDelete
  39. Hi sir, why we need parameters like h0,h1,h2,h3,h4, and then wires u used i am not getting that sir,if u don't mine please explain in brief sir

    ReplyDelete
  40. can you please give me the verilog code for denoising ecg using wavlelet transform

    ReplyDelete
  41. whats the cuttoff frequency of this filter??

    ReplyDelete
  42. For all the people who are referring this code, here are a few responses:

    1. Multiply or Divide
    Multiply by integer (<< - Left shift ) ---- a * B
    Divide by integer (<< - Right Shift ) ---- a / B
    Multiply by fraction (<< - Right shift - divide it ;) ) ---- a / (1/B)

    Why ? The coefficients are generally in the range -1 < B < 1.

    2. The coefficients of the filters are h0, h1, h2, h3, etc.

    3. The above code is not 4 tap FIR Filter (clue: d11, d12, d13 and d14) 4 DFF's are used.

    4. Follow the pattern and design higher order FIR filters.

    ReplyDelete
  43. 16 bit fir fliter code please

    ReplyDelete
  44. 16 bit fir fliter verlig code

    ReplyDelete
  45. some more information is here
    https://rtldigitaldesign.blogspot.com/2016/11/verilog-code-for-fir-filter.html

    ReplyDelete
  46. wallace tree multiplier in fir filter verilog code

    ReplyDelete
  47. when we implement it in xilinx and then synthesize it will generate bit file and then we should burn on FPGA through Impact my question is how we apply signal of our desired frequency as we know the frequency of SPARTAN 3E 72MHz

    ReplyDelete