Monday 31 March 2014

Reading Image File using HDL

Storing image file onto FPGA has two main steps

  1. Converting image file format to co-efficient file format(COE format)
  2. Storing the COE image file using BRAM(block ram IP core)








1. Converting image to COE format:

In this tutorial we will try and convert JPEG image to COE format using a matlab code. It can also be used for file formats  as bmp, gif, and tif too. Locate the image to be converted in the working directory and run the program given below. After successful execution the program will ask for the location of the image to be converted following which the converted image file will be stored in the same working directory. Copy this .COE file and don't make any alteration to it.  (Here make sure that the image file if of size 240x160)
















































This format is a RAW image file which saves the values of the pixel in an array(1 Dimension). First two lines of this file are used to indicate the data type(hex/binary/octal etc) and second line marks the beginning of  the pixel values. 


2. Storing COE file in BRAM IP core

Create a new project in Xilinx and in the new source file wizard click on IP(core generator and architecture) . Name this file as "mymemory" and click next


Select Block Memory Generator v2.8 in the submenu RAMs & ROMs under the Memories & Storage Select Next, then Finish.



The .coe file produced by  will contain 240×160 = 38,400 bytes. Following the procedure described we can use the Core Generator to create a read only block memory component "mymemory" of size 240x160, which is 8 bits wide with a depth of 38400 .





















Click on Load Int File and click on Browse. Place the COE file generated in the location where the browsers points to. It will be in the "ipcore_dir" folder of your project.





















Once the file is loaded we have an option to view the contents of your COE file . To view your coe file click on "show" . Verify if the width and the depth of your image file matches with the one which you have provided for the IP core. Once verified click next and generate. It might take time for the IP BRAM to get generated after which it will appear as a module in your project directory. After successful creation of IP BRAM and COE files your image is now ready to be operated on. You can perform all types of image processing algorithms like smoothing,edge detection , noise reduction etc. Try all these steps and check if you got it right. queries are welcome . Thank you



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8 comments:

  1. after the module has been created how do we display the image on a display

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  2. Hello sir,

    i am getting a error

    cannot find radix with name: matrix_intialization_radix

    Thankyou so much such a wonderful blog.:)

    must say u are doing a great job..:)

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    1. http://verilog-code.blogspot.com/2018/08/books-to-buy-for-beginners-verilogvhdl.html

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    2. Even I am facing the same error. Please help.

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  3. This comment has been removed by the author.

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  4. Can I use this method on a bin file that I have generated from a bmp file using matlab ?

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    1. http://verilog-code.blogspot.com/2018/08/books-to-buy-for-beginners-verilogvhdl.html

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