Tuesday 27 August 2013

DSP butterfly Unit

Hello friends. You must be aware of the applications of Verilog coding & its significance in different domain. From the last few months i was working on one such use of Verilog in DSP.  Signals & systems   is my all time favorite subject & its the one with lot of applications & used in many products like mobiles, tv, image processing etc. The list is long though  :) We will talk about one such DSP module today " The FFT Butterfly unit " . Before you read this post i suggest you to go through the FFT algorithm (DIT/DIF) so that it will be easy for you to understand the code.  Fast Fourier transform is used to convert a signal from time domain to frequency & this is needed so that you can view the frequency components present in a signals . If you know the frequency components present in a signals you can play with the signals :) Lets say, u want to design a low pass filter and want to decide on the cut off frequency of the filter . If you have the frequency domain details for a signals u can clearly identify the frequency components which u want to retain & the ones which u want to take out. Well let us not discuss this topic in detail here , but if you are still interested than you can refer to my short notes on FFT here:
 Fourier analysis

The figure below shows the FFT implementation using radix 2 algorithm.





























this is a 8 point FFT implementation using the butterfly unit, The butterfly unit is the heart of FFT algorithm . From the figure u can see that if we are done with the butterfly unit we are 70% done with the FFT coding.
Okie now lets start the coding for butterfly unit . The back box model of the butterfly will have 2 complex inputs & 2 complex outputs
The second input gets multiplied with the twiddle factor i.e (wr + j wi ) first. So before you start coding you must have the code written for complex number multiplication. Once you are done with the multiplication the next step is to do addition . You can do this by simple CLA (carry look ahead adders) . Output Z1 is obtained by adding the result of multiplication i.e(b1+jb2) * (Wr+jWi) to the first number i.e a1+ja2. And output Z2 is obtained by subtracting the multiplied product with the first number . To put it in mathematical form


Z1r+jZ1i= (b1+jb1)*(Wr+jWi) + (a1+ja2)

Z2r+jZ2i= (b1+jb1)*(Wr+jWi) - (a1+ja2)


If the result is analysed proerly u will discover that we need a complex multiplier ( which has 4 normal multipliers ) & 4 CLA units . To put the process in orderly manner we have to proceed in steps like this
1> read 2 complex numbers & the twiddle factor 
2>multiply 2nd number with the twiddle factor
3> add the product to 1st number to get the first o/p
4>Subtract the product to 1st number to get the first o/p

We are done. Here is the code for the Butterfly unit & the results of simulation & the RTL schematic

CODE:

RTL SCHEMATIC FOR THE CODE:






















Link for the coupons : Here

Black Box model:
























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49 comments:

  1. Can you plz provide me help regarding FFT coding . its my project for this year

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    Replies
    1. The butterfly unit is already been explained on this site with the source code. You can use this same module & use it for FFT. Here is how you do it:
      1> modify the butterfly for stage1 stage2 & stage3 operations
      2> check individual stage output & verify the answers
      3>Declare the twiddle factors as Parameters .
      for example, if you are doing a 8 point FFT u can declare the twiddle factors as :
      parameter w0r=8'b1;
      parameter w0i=8'b0;
      parameter w1r=8'b10110101;
      parameter w1i=8'b01001011;
      parameter w2r=8'b0;
      parameter w2i=8'b11111111;
      parameter w3r=8'b01001011;
      parameter w3i=8'b01001011;


      All the best :)

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    3. Could you please explain how to modify for Stage1, Stage2 and Stage3. Thanks in advance

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    4. Can you please tell me why have you used one's complement instead of two's complement to represent negative nos?

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    5. how can we generate twiddle factors for the same?

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  2. SIr i want this coding...My mail id way2madhanm@gmail.com

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    Replies
    1. You can use the code from the blog itself . save it as image file and write the same code using xilinx

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  3. Sir can you explain the value of twiddle factor for 8-point dft

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    Replies
    1. You can refer any DSP book for twiddle factor calculations , Its quite easy to do for any N point FFT.
      For a N point FFT its given by :

      e^-j2pi/N=cos(2pi/N)-jsin(2pi/N)

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    2. since real part and imag part are less than one ...how you represent it in binary?

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    3. use floating point representation (iee754 standard)

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    4. on simulation all inputs and outputs are shown as binary numbers . If i want to change them to real numbers what should i do?

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    5. There is no such options , You have to verify your answers in 754 format. There are many tools online which can give you the floating point value in ieee754 to normal number , Use that for verification

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  4. sir can you send me a code for butterfly where all input and output are real numbers not binary ......my email id ankeshnehara@gmail.com

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  5. hai sir
    i have simulated the above codei am getting error ERROR:HDLCompilers:87 - "8point.v" line 147 Could not find module/primitive 'xor21'
    ERROR:HDLCompilers:87 - "8point.v" line 151 Could not find module/primitive 'xor21'
    ERROR:HDLCompilers:87 - "8point.v" line 155 Could not find module/primitive 'xor21'
    ERROR:HDLCompilers:87 - "8point.v" line 159 Could not find module/primitive 'xor21'
    ERROR:HDLCompilers:87 - "8point.v" line 164 Could not find module/primitive 'xor21'
    ERROR:HDLCompilers:87 - "8point.v" line 172 Could not find module/primitive 'xor21'
    ERROR:HDLCompilers:87 - "8point.v" line 182 Could not find module/primitive 'xor21'
    ERROR:HDLCompilers:87 - "8point.v" line 143 Could not find module/primitive 'xor21'
    ERROR:HDLCompilers:87 - "8point.v" line 147 Could not find module/primitive 'xor21'
    ERROR:HDLCompilers:87 - "8point.v" line 151 Could not find module/primitive 'xor21'
    ERROR:HDLCompilers:87 - "8point.v" line 155 Could not find module/primitive 'xor21'
    can u help me pls

    regards
    bharath kumar m
    bharathreddy.rymec@gmail.com

    ReplyDelete
    Replies
    1. Hie . you have to write modules for all basic gates. "xor21" means its a two input xor gate. similarly write the code for other gates used like or , and etc

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    2. the above code is for 8 point right??

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    3. The code is for a butterfly unit, you can use this to build 8 point FFT

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  6. i am also looking for 8-point fft code.so pls any ne help me.If anybody having the code send to gurram836@gmail.com

    thank u ...

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  7. sir,plz give code for 8pt fft also..how to modify this butterfly code

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  8. sir, plz give code for 16 point DIF

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  9. This comment has been removed by the author.

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  10. sir pls send me code for 8 point fft
    pls sir its urgent
    pls send it to ksamaikya@gmail.com

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  11. please provide the code for 8 point fft.I am in urgent need.please forward it at suyashvikramagrawal@gmail.com

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  12. i am not ableto code the 64 point fft so if anybody having the code of64 point fft then plz send mi on umeshbirangal@gmail.com

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  13. can we use this as a basic verilog project?

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  14. the multiplier output is 64 bit in contrast the input given to cla32 is 32 bit....whats the solution??

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  15. why are you performing b<= -d2 -1 when cin=1

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  16. hi I am trying to write verilog code for 8 -point fft. you mentioned twiddled factors can be declared as

    parameter w0r=8'b1;
    parameter w0i=8'b0;
    parameter w1r=8'b10110101;
    parameter w1i=8'b01001011;
    parameter w2r=8'b0;
    parameter w2i=8'b11111111;
    parameter w3r=8'b01001011;
    parameter w3i=8'b01001011;

    but the input to butterfly unit twiddle factors are 32 bit ? so the above declaration works

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  17. If possible can you send me the code for 8-point fft. my email id sabhp143@gmail.com

    ReplyDelete
    Replies
    1. U have 8 point FFT cod send me to
      vj26869@gmail.com

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  18. the code simulated well..but when i am entering the inputs a1,b1,a2,b2,
    the outputs are always in high impedance there is no output displayed..
    can u tell me the input and twiddle factor values to get the correct output..plz

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  19. sir i am doing my PG project is 32 point FFT algorithm .please send the verilog code for 32 point fft algorithm code in verilog.my email is venkatanaidubakuru@gmail.com

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  20. As far as the program is concerned it the equation would be (a1+jb1) & (a2+jb2).
    The lower part also should be of the form p-qW and not qw-p.

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  22. Hi, can someone please explain why a2 and b2 are being multiplied by the twiddle factor? I thought it should be b1 and b2. Thanks!

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  23. in synthesis it is showing more no of IOBS ,,,,what to do,,,i removed some input like w,,,zi_c like term ,,still it is more

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  24. Can anyone please explain why you have used (z[63]=z[62];) in the multiplier module? I couldn't understand this line

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  25. Hello there,

    Thanks so much for providing this code written in a good and understandable format. I am having a problem in understanding that why we are taking Cout from butterfly unit as we are not going to use it in next butterfly unit while implementing complete 3 stage butterfly diagram?

    Looking forward.

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  26. when executed there is no error but i am getting wrong outputs

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  27. can you plzz provide the code for 16 point fft using dif algorithm. plz send it at subhadipporia@gmail.com

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  29. can you please send me the 8 point fft code at muladas420@gmail.com

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  30. sir may i know for which point is this fft program belong to

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  31. Output of Multiplier is 64 bit, something wrong here.. Suggest what changes need to do.

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  32. The code is only a single butterfly unit, not an entire FFT

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  33. Sir can u send 8 point FFT code to vj26869@gmail.com

    ReplyDelete