FIR FILTER DESIGN USING VERILOG

     FIR filters are is widely used in different applications such as biomedical, communication and control due to its easily implementation, stability and best performance. Its simplicity makes it attractive for many applications where it is need to minimize computational requirements.

Filters play an important role for removal of unwanted signal or noise from original input signal by removing the selected frequencies from incoming signal. They became much popular due to the increase of the digital signal processing.

 Comparison between FIR and IIR Filters

The non recursive (FIR) and recursive (IIR) filters have different characteristics for numbers of applications. The non recursive filters are chosen due to its best performance of numerical operations, differentiation and integration. The table 2.1 below shows the comparison between FIR and IIR filters.

IIR	FIR
More Efficient	Less Efficient
Analog Equivalent	No Analog Equivalent
May Be Unstable	Always Stable
Non-Linear Phase Response	Linear Phase Response
No Efficiency Gained by Decimation	Decimation Increases Efficiency

VERILOG CODE FOR FIR FILTER

// main module FIR

module filterfir(clk,rst,x,dataout);

input [7:0]x;

input clk,rst;

output [9:0]dataout;

wire [7:0]d1,d2,d3;

wire [7:0]m1,m2,m3,m4,m5;

wire [7:0]d11,d12,d13,d14;

parameter h0=3'b101;

parameter h1=3'b100;

parameter h2=3'b011;

parameter h3=3'b010;

parameter h4=3'b001;

assign m1=x>>h0;

dff u2(clk,rst,x,d11);

assign m2=d11>>h1;

assign d1=m1+m2;

dff u4(clk,rst,d11,d12);

assign m3=d12>>h2;

assign d2=d1+m3;

dff u6(clk,rst,d12,d13);

assign m4=d13>>h3;

assign d3=d2+m4;

dff u8(clk,rst,d13,d14);

assign m5=d14>>h4;

assign dataout=d3+m5;

endmodule

module dff(clk,rst,d,q);// sub module d flipflop

input clk,rst;

input [7:0]d;

output [7:0]q;

reg [7:0]q;

always@(posedge clk)

begin

if(rst==1)

begin

q=0;

end

else

begin

q=d;

end

end

endmodule

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Types Of Adders with Verilog Code

Adders in Vlsi are basic components for an ALU . There are N number of adders each with their own advantages & disadvantages. When two numbers are to be added and if each of them is of N bits than we can add them in Two different ways :

1. Serial
2. Parallel

In serial addition the LSB's are added first than the carry created are propagated to the next higher bits. Whereas in parallel addition every it added in parallel without waiting for carry and different algorithms are used to compensate for the carry.

                        

                          Carry bits are to handled properly so that the resulting answer after addition is correct.But as we know that for each addition there can be a carry generated can it has to be accounted for. When we try doing this the major criteria to be kept in mind are propagation time and time taken to calculate the carry. Here are few Verilog codes for different types of adders:

>>>Verilog code for Half adder

>>>Verilog code for Full adder

>>>Verilog code for Parallel adder

>>>Verilog code for CLA(carry look ahead affer)

>>>Verilog code for RCA(Ripple carry adder)

>>>Verilog code for 32 Bit Pipelined Floating Point Adder 

>>>Verilog code for BCD Adder 

>>> Verilog code for Carry Save Adder 

>>>Verilog Code for Carry Select Adder

Verilog code for Barrel shifter

The architecture of the arm 7 is quite unique & is optimized for speed and area. To talk about its bus structure which is patented by Arm called the Amba bus is completely designed by the company itself. Tough its a difficult task to code and design for the entire ARM here is a small module of ARM called the Barrel Shifter as circled in the figure below. The task of the Barrel sifter is to do simple shift & roate operation on the second operands . Shifting a bit to right by one position means the same as to dive the number bu the base 2 . Conversely left shift by one position implies multiplying by 2. So this Shifter reduces the task of the ALU in total. Here is the Verilog code for the Barrel Shifter


module barrel_shifter(d,out,q,c); // Main module of 8-Bit Barrel shifter

  input [7:0]d;

  output [7:0]out,q;

  input[2:0]c;

  mux m1(q[0],d,c);

  mux m2(q[1],{d[0],d[7:1]},c);

  mux m3(q[2],{d[1:0],d[7:2]},c);

  mux m4(q[3],{d[2:0],d[7:3]},c);

  mux m5(q[4],{d[3:0],d[7:4]},c);

  mux m6(q[5],{d[4:0],d[7:5]},c);

  mux m7(q[6],{d[5:0],d[7:6]},c);

  mux m8(q[7],{d[6:0],d[7:7]},c);

  assign out=q;

endmodule

module mux(y,d,c); // Sub module of 8-Bit barrel shifter

  input[7:0]d;

  output y;

  reg y;

  input [2:0]c;

  always @ (c)

  begin

    if (c==3'b000)

      y = d[0];

    else if (c==3'b001)

      y = d[1];

      else if (c==3'b010)

      y = d[2];

      else if (c==3'b011)

      y = d[3];

      else if (c==3'b100)

      y = d[4];

      else if (c==3'b101)

      y = d[5];

      else if (c==3'b110)

      y = d[6];

      else if (c==3'b111)

      y = d[7];

    end

  endmodule

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DSP butterfly Unit

Hello friends. You must be aware of the applications of Verilog coding & its significance in different domain. From the last few months i was working on one such use of Verilog in DSP.  Signals & systems   is my all time favorite subject & its the one with lot of applications & used in many products like mobiles, tv, image processing etc. The list is long though  :) We will talk about one such DSP module today " The FFT Butterfly unit " . Before you read this post i suggest you to go through the FFT algorithm (DIT/DIF) so that it will be easy for you to understand the code.  Fast Fourier transform is used to convert a signal from time domain to frequency & this is needed so that you can view the frequency components present in a signals . If you know the frequency components present in a signals you can play with the signals :) Lets say, u want to design a low pass filter and want to decide on the cut off frequency of the filter . If you have the frequency domain details for a signals u can clearly identify the frequency components which u want to retain & the ones which u want to take out. Well let us not discuss this topic in detail here , but if you are still interested than you can refer to my short notes on FFT here:
 Fourier analysis

The figure below shows the FFT implementation using radix 2 algorithm.

this is a 8 point FFT implementation using the butterfly unit, The butterfly unit is the heart of FFT algorithm . From the figure u can see that if we are done with the butterfly unit we are 70% done with the FFT coding.
Okie now lets start the coding for butterfly unit . The back box model of the butterfly will have 2 complex inputs & 2 complex outputs

The second input gets multiplied with the twiddle factor i.e (wr + j wi ) first. So before you start coding you must have the code written for complex number multiplication. Once you are done with the multiplication the next step is to do addition . You can do this by simple CLA (carry look ahead adders) . Output Z1 is obtained by adding the result of multiplication i.e(b1+jb2) * (Wr+jWi) to the first number i.e a1+ja2. And output Z2 is obtained by subtracting the multiplied product with the first number . To put it in mathematical form

Z1r+jZ1i= (b1+jb1)*(Wr+jWi) + (a1+ja2)

Z2r+jZ2i= (b1+jb1)*(Wr+jWi) - (a1+ja2)

If the result is analysed proerly u will discover that we need a complex multiplier ( which has 4 normal multipliers ) & 4 CLA units . To put the process in orderly manner we have to proceed in steps like this

1> read 2 complex numbers & the twiddle factor 

2>multiply 2nd number with the twiddle factor

3> add the product to 1st number to get the first o/p

4>Subtract the product to 1st number to get the first o/p

We are done. Here is the code for the Butterfly unit & the results of simulation & the RTL schematic

CODE:

RTL SCHEMATIC FOR THE CODE:

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Black Box model:

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RTL Schematic/Technology schematic

RTL Code:

Hello there. I have been posting about the Verilog coding since a month & just to add to it will deal with the RTL coding today for your design. :)  This post is to completely understand and analyze the RTL code which includes the RTL schematic and the Technology schematic. Having completed your Verilog coding the next step which you all know is to simulate it and verify if the design is working fine. Up to this point in the flow of design process we are still in the software part of coding. To view the code in terms of hardware you will have to move a step ahead and go for “Synthesis “ .  To put it in simple terms synthesis implies the hardware equivalent of your written Verilog code. There are inbuilt synthesis tool which are part of Xilinx & the one which is used is the XST tool. The job of the synthesis tool is to read the code written in Verilog/hdl and with the aid of the library files it has to convert this code to a hardware description netlist. The figure below shows how the process works.

 

Xst tool is quite user friendly to use & it produces the synthesized design just by a few clicks. But one thing is always true, the easier it looks the more complex program is running behind. J we will start now with the Xilinx RTL coding by considering a simple code(D flip flop) and lets try to create both the technology schematic and RTL schematic for it. The Verilog code for D flip flop is given below

module dff(d,clk,rst,en,q,qbar

    );

input d;

input clk;

input rst; // reset

input en; //enable

output q;

output qbar;

reg q;

wire qbar;

assign qbar=!q;

always @(posedge clk)

begin

if(rst) //if reset is high make q=0

q=0;

else if(en)

begin // if reset is low and en is high make ff transparent

q=d;

end

end

endmodule

The objective is not to analyze the code now but to check how the code is mapped to hardware. You can copy this code from here & work in parallel as I take you through the RTL coding. Okie , now change the mode of Xilinx from simulation to implementation mode.  You will find the Synthesis XST option on the right side as show. 

In the Processes pane, right-click Synthesize - XST, and select Process Properties to open the Synthesis

 Options dialog box. Set the Keep Hierarchy option to Yes as shown. 

This is to ensurethat we have the flexibility of viewing the hardware for every module is our design(in case you have many modules in your design). Now just double click on the “View RTL schematic” & you will get a pop up window like this one

Just say OK and the next window will pop up. Select the hierarchical block named dff, and move it to Selected Elements using the Add button, and then click Create Schematic. we are done J the RTL for our code is now generated. It must look like this one

Well now comes the interesting part. J the figure shows the internal and external signals. The border here for this block has a triangle at each edge which indicates that this block is not a primitive but part of our hierarchical design. if you double click on this you will get the exact hardware equivalent of the code . it has a block named “fdre” which is a D flip flop from the library about which we talked about earlier and a "not" gate is present along with it .

   

Now if you place the mouse cursor on any of these elements or the signals the details are displayed. Try it for yourself. For example if you place the cursor on the “fdre” is will display “BLOCK=q,Type=fdre,INT=0”. If you try the same with the signal it will display the number of pins connected to that particular signals. We are now dealing with a simple design (dff)so there are no pins that are invisible. If you try with a complex design you will discover that few pins will be mentioned invisible.

Instead of placing the cursor if you click on a signal you find two symbols indicating the start and end point of the signal.

The RTL schematic generated by the XST tool will be saved in the “.ngr” file format and this schematic is independent of the target device where you want to test your design, in our case its Spartan-3 fpga). If you want to view the exact hardware as it will be mapped to your target FPGA device you will have to go for “view Technology schematic and repeat the same process.

The file format for technology schematic is “.ngc”. Here is how your technology schematic will look like & notice that this one is different from the RTL schematic.

Clearly the input signals are first saved using buffers as it can be noticed. This is necessary because in real time implementation it will be necessary to save the inputs in buffers and then propagate them to the internal design. This avoids the synchronization problems between the FPGA and the inputs devices. 

 Well I hope this post was useful to you, if so do write back to me 

BYE :) 

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EXPLORING THE SCHEMATIC VIEWER WINDOW

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 The schematic Viewer window is given here with reference to the each icon present to assist you to speed up your RTL coding skills :

1. The schematic window is the main window where you explore your design by adding or removing elements.

2. This toolbar contains the functions specific to the Schematic Viewer.

3. This panel contains two types of information: objects visible on the schematic (instances, pins and signals) and object properties. For example, you can select a BRAM primitive in your schematic and see all its properties, including BRAM initialization values.

Note: You must select the View by Category tab to see this panel.

4. This toolbar contains functions shared by different graphical tools such as Zoom

Zoom options :