FSM-Finite State Machine

FSM: Finite state machine
State machine is simply another name for sequential circuits. Finite refers to the fact that the number of states the circuit can assume if finite. A synchronous clocked FSM changes state only when a triggering edge (or tick) occurs on the clock signal.

This is the structure of any FSM in general .

There are two main types of FSMs

l  Mealy (output is function of state and inputs)

l  Moore (output is only function of state)

Mealy machine:

Moore machine:

To summarize a Mealy model is a FSM whose output depends on the current state and also the inputs whereas in the Moore model the output depends only on the current state. The state memory indicates storage which had flip flops to do the task. The Next state logic and the output logic both are computational circuits and the state memory is sequential. Here is a table to compare the two models

l  Mealy machines have less states compared to Moore l  Moore machines are safer to use as its output is synchronous with the clock alone unlike in Moore model where a asynchronous input may change the output l  Mealy machines react faster to inputs l  In Moore machines, more logic may be necessary to decode state into outputs – there may be more gate delays after clock edge

In simple terms a FSM consist of a sequential part and two combinational parts. The task of the sequential part (state memory) is to store the state of the circuit. The combinational parts are used to calculate the next state logic and the output logic. Did u get it? Is so try to decode these circuits and classify them as Mealy or Moore. J

Circuit 1

   Mealy or Moore?

Circuit 2

 

Mealy or Moore?

Circuit 3

Mealy or Moore?

Circuit 4

Mealy or Moore?

As an example for a simple FSM with verilog code for a sequence detector :

Problem statement : Write a FSM in HDL for sequence detector which will detect the sequence "0111"

VERILOG CODE:

module sequence_0111(clock, reset, in_bit, out_bit

    );

  input clock, reset, in_bit;

  output out_bit;

  reg [2:0] state_reg, next_state;

  // State declaration

  parameter    reset_state  =  3'b000;

  parameter    read_zero =   3'b001;

  parameter    read_0_one =   3'b010;

  parameter    read_zero_one_one = 3'b011;

  parameter    read_zero_one_one_one= 3'b100;

  // state register

  always @ (posedge clock or posedge reset)

     if (reset == 1) 

        state_reg <= reset_state; 

     else  

        state_reg <= next_state;

  // next-state logic

always @ (state_reg or in_bit) 

    case (state_reg)

        reset_state: 

              if (in_bit == 0) 

                  next_state = read_zero; 

              else if (in_bit == 1) 

                  next_state = reset_state;

              else next_state = reset_state;

        read_zero: 

              if (in_bit == 0) 

                  next_state = read_zero; 

              else if (in_bit == 1) 

                  next_state = read_0_one;

              else next_state = reset_state;

        read_0_one: 

              if (in_bit == 0) 

                  next_state = read_zero; 

              else if (in_bit == 1) 

                  next_state =  read_zero_one_one;

              else next_state = reset_state;

 read_zero_one_one: 

            if (in_bit == 0) 

                next_state = read_zero;

            else if (in_bit == 1) 

                next_state = read_zero_one_one_one;

            else  next_state = reset_state;

      read_zero_one_one_one: 

            if (in_bit == 0) 

                next_state = read_zero; 

            else if (in_bit == 1) 

                next_state = reset_state;

            else next_state = reset_state;

        default: next_state = reset_state;

  endcase

assign out_bit = (state_reg == read_zero_one_one_one)? 1 : 0;

endmodule

RTL :

Simulation results:

Test fixture for sequence detector :

module test_ma_sequence;

// Inputs

reg clock;

reg reset;

reg in_bit;

// Outputs

wire out_bit;

// Instantiate the Unit Under Test (UUT)

sequence_0111 uut (

.clock(clock), 

.reset(reset), 

.in_bit(in_bit), 

.out_bit(out_bit)

);

initial begin

// Initialize Inputs

clock = 0;

reset = 0;

in_bit = 0;

// Wait 100 ns for global reset to finish

#10;

reset = 1;

in_bit = 0;

#10;

reset = 0;

in_bit = 0;

#10;

        

 reset = 0;

in_bit = 1;

#10;

reset = 0;

in_bit = 1;

#10;

reset = 0;

in_bit = 1;

#10;

// Add stimulus here

reset = 1;

in_bit = 1;

#10;

reset = 0;

in_bit = 0;

#10;

reset = 0;

in_bit = 1;

#10;

reset = 0;

in_bit = 1;

#10;

reset = 0;

in_bit = 1;

#10;

end

 always begin #5 clock=~clock; end    

endmodule

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