vlsi projects using verilog code

• FPGA based CAN Bus Controller design using Verilog/VHDL
• FPGA based CAN Bus Protocol Analyzer design using Verilog/VHDL
• FPGA based “Drive By Wire” Electronic Control Unit for Vehicles
• FPGA based “Throttle By Wire” Electronic Control Unit for Vehicles
• FPGA based “Break By Wire” Electronic Control Unit for Vehicles
• FPGA based “Steering By Wire” Electronic Control Unit for Vehicles
• FPGA based Flexray Bus controller design using Verilog/VHDL
• FPGA based Flexray Bus Guardian system design using Verilog/VHDL
• High Definition HDTV Data Encoding and Decoding using Reed Solomon Code
• Design & Implementation of Noise / Echo canceler using FPGA with Verilog/VHDL
• 8/16/32 Point Fast Fourier Transform Algorithm using FPGA with Verilog/VHDL
• VLSI Implementation of Booths Algorithm using FPGA with Verilog/VHDL
• Design of a Multi-Mode Receive Digital-Front-End for Cellular Terminal RFIC
• VLSI implementation of canonical Huffman encoder/decoder algorithm using FPGA with Verilog/VHDL code
• VLSI implementation of Steganography using FPGA with Verilog/VHDL code
• 16 Bit fixed point DSP Processor using FPGA with Verilog/VHDL
• VLSI Implementation of AHDB (Adaptive Huffman Dynamic Block) Algorithm
• Fuzzy based PID Controller using VHDL for Transportation Application
• Full-Rate IEEE 802.11a Compliant Digital Baseband Transmitter on FPGA
• An Area-Efficient Universal Cryptography Processor for Smart Cards
• FPGA Based Power Efficient Channelizer for Software Defined Radio
• Superscalar Power Efficient Fast Fourier Transform FFT Architecture
• High-Speed Architecture for Reed-Solomon Decoder/Encoder
• Fault Secure Encoder and Decoder for Nano-memory Applications
• High-Speed Booth Algorithm Encoded Parallel Multiplier Design
• Implementation of IEEE 802.11a WLAN Baseband Processor
• FPGA based Generation of High Frequency Carrier for Pulse Compression using CORDIC Algorithm
• Cryptography AES/DES Encryption Algorithm using FPGA with Verilog/VHDL code
• VLSI Design & Implementation of Viterbi Algorithm-Encoder/Decoder using FPGA with Verilog/VHDL code
• Dynamic/Deficit Round Robin Algorithm using FPGA with Verilog/VHDL code
• UART Asynchronous Transmitter/Receiver using FPGA with Verilog/VHDL code
• RS-232 Transmitter/Receiver using FPGA with Verilog/VHDL code
• Asynchronous Serial controller using FPGA with Verilog/VHDL code
• Universal Serial Bus USB Device Controller using FPGA with Verilog/VHDL code
• Multichannel I2S Audio Controller using FPGA with Verilog/VHDL code
• Huffman Encoder/Decoder using FPGA with Verilog/VHDL code
• Programmable 16-Tap Low-power FIR Filter using FPGA with Verilog/VHDL code
• 2-D Convolution Engine using FPGA with Verilog/VHDL code
• VGA/LCD Controller using FPGA with Verilog/VHDL code
• Cyclic Redundancy Check ECRC/LCRC Error Check using FPGA with Verilog/VHDL code
• PCI Express Interface Controller using FPGA with Verilog/VHDL code
• Highspeed USB 2.0/Superspeed USB 3.0 Transmitter and Receiver using FPGA with Verilog/VHDL
• VLSI Progressive Coding for Wavelet-based Image Compression
• Low Power Test Pattern Generator Using a Variable-Length Ring Counter
• Deviation-Based LFSR Reseeding for Test-Data Compression
• Hardware implementation of Variable Precision Multiplication on FPGA
• Novel Area-Efficient FPGA Architectures for FIR Filtering With Symmetric Signal Extension
• Power Optimization of Linear Feedback Shift Register (LFSR) for Low Power BIST

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