Vedic
Multipliers:
You
all must have heard of Vedic mathematics and I am sure you must have tried few Vedic
logic to add/multiply/divide etc.. What is more interesting about Vedic is the
logic behind it. Ever since it has come into existence people have tried coming
up with their own set of Vedic hardware keeping the low power issues and the
area constraints. I came across one such logic using Vedic maths for fast
multiplications and browsed few papers related to it. Interestingly I noticed
that its quite simple for anyone to design their own Vedic hardware multiplier
using Verilog. So I tried doing it myself using few papers and resources. Guess
what? it worked
The
Vedic logic I used is the “Urdhva Triyakbhyam Sutra” . If you google it I am
sure u will get the logic so i will not explain much about logic here but
instead will start with the hardware design of Vedic multiplier. Here is
snapshot of the logic which is easy to understand
The
figure shows how to multiply two 2 bit numbers using Urdhva Triyakbhyam Sutra. Now with this logic we have to convert it
to a equivalent hardware. Two bit multiplication is equivalent to a “and” gate so my first part is over. Next part is to add two bits which is nothing but a
half adder and for our logic we need two half adders. U can easily code for a
half adder, If not its available here http://verilog-code.blogspot.in/p/verilog-codesprojects.html
. Let’s start
with the coding now and make sure that you have understood the logic well
before you proceed reading .
To start with the design
has two stages:
1> Multiplier stage
using “and” gates and we need four such gates
2> half adders and two
such adders
[Note: the carry of first
adder must be added to the second adder]
This is my black box model
showing only the inputs and outputs:
showing only the inputs and outputs:
