Refer to "HDL progamming using Verilog and Vhdl " by botros for booth multiplier logic.
or watch this video
CODE:
module booth (X, Y, Z,en);
input signed [15:0] X, Y;
input en;
output signed [31:0] Z;
reg signed [31:0] Z;
reg [1:0] temp;
integer i;
reg E1;
reg [15:0] Y1;
always @ (X, Y,en)
begin
Z = 32'd0;
E1 = 1'd0;
for (i = 0; i < 16; i = i + 1)
begin
temp = {X[i], E1};
//The above statement is catenation
Y1 = - Y;
//Y1 is the 2’ complement of Y
case (temp)
2'd2 : Z [31 : 15] = Z [31 : 15] + Y1;
2'd1 : Z [31 : 15] = Z [31 : 15] + Y;
default : begin end
endcase
Z = Z >> 1;
/*The above statement is a logical shift of one position to
the right*/
Z[31] = Z[30];
/*The above two statements perform arithmetic shift where
the sign of the number is preserved after the shift. */
E1 = X[i];
end
if (Y == 16'd32)
/*If Y = 1000; then according to our code,
Y1 = 1000 (-8 not 8, because Y1 is 4 bits only).
The statement sum = - sum adjusts the answer.*/
begin
Z = - Z;
end
end
endmodule
or watch this video
CODE:
module booth (X, Y, Z,en);
input signed [15:0] X, Y;
input en;
output signed [31:0] Z;
reg signed [31:0] Z;
reg [1:0] temp;
integer i;
reg E1;
reg [15:0] Y1;
always @ (X, Y,en)
begin
Z = 32'd0;
E1 = 1'd0;
for (i = 0; i < 16; i = i + 1)
begin
temp = {X[i], E1};
//The above statement is catenation
Y1 = - Y;
//Y1 is the 2’ complement of Y
case (temp)
2'd2 : Z [31 : 15] = Z [31 : 15] + Y1;
2'd1 : Z [31 : 15] = Z [31 : 15] + Y;
default : begin end
endcase
Z = Z >> 1;
/*The above statement is a logical shift of one position to
the right*/
Z[31] = Z[30];
/*The above two statements perform arithmetic shift where
the sign of the number is preserved after the shift. */
E1 = X[i];
end
if (Y == 16'd32)
/*If Y = 1000; then according to our code,
Y1 = 1000 (-8 not 8, because Y1 is 4 bits only).
The statement sum = - sum adjusts the answer.*/
begin
Z = - Z;
end
end
endmodule
output is not coming correctly.
ReplyDeleteI gave inputs: X = 16'b0000000000000100;
Y = 16'b0000000000000011;
en = 1;
Expected output is Z=00000000000000000000000000001100.
However, obtained output is 00000000000000100000000000000110
Can you explain how.
you do in table form then you will obtain the same output
Deletewrong result
ReplyDeletewrong result..not synthesizable
ReplyDeleteplease provide the testbench of this code
ReplyDeletehttp://verilog-code.blogspot.com/2018/08/books-to-buy-for-beginners-verilogvhdl.html
DeleteThis comment has been removed by the author.
ReplyDeleteThis would give the correct answer
ReplyDeletemodule boothmul(X, Y, Z,en);
input signed [15:0] X, Y;
input en;
output signed [31:0] Z;
reg signed [31:0] Z;
reg [1:0] temp;
integer i;
reg E1;
reg [15:0] Y1;
always @ (X, Y,en)
begin
Z = 32'd0;
E1 = 1'd0;
Y1 = - Y;
Z[15:0]=X;
for (i = 0; i < 16; i = i + 1)
begin
temp = {X[i], E1};
case (temp)
2'd2 : Z [31 : 16] = Z [31 : 16] + Y1;
2'd1 : Z [31 : 16] = Z [31 : 16] + Y;
default : begin end
endcase
Z = Z >> 1;
Z[31] = Z[30];
E1 = X[i];
end
end
endmodule
can you pls give me test bemch for this
DeleteIt does not.
DeleteConsider 2bit input : 11 * 11 (answer should be 1001) with the above code we get 0001
What does this mean?- temp = {X[i], E1}
ReplyDeleteIT IS CONCATINATION
Deletehttp://verilog-code.blogspot.com/2018/08/books-to-buy-for-beginners-verilogvhdl.html
That is concating the Q0 and Q(-1) for performing the algorithm
ReplyDeleteplease provide 32 bit and 64 bit also
ReplyDeletehttp://verilog-code.blogspot.com/2018/08/books-to-buy-for-beginners-verilogvhdl.html
Deletewhat is en in this?
ReplyDeleteplz provide the radix8 booth multiplier in vhdl1
ReplyDeleteyou got any code for radix 8 please reply
DeletePlz provide the verilog code for 8 bit using modified booth's algorithm
ReplyDeleteCould u please post test bench
ReplyDeletehow to write verilog code for vedic multiplier in sequential mode?
ReplyDeleteCould u please post test bench
ReplyDeleteat the end you did this.... i didn't get it what is the purpose of this part and what is going on this part
ReplyDeleteif (Y == 16'd32)
/*If Y = 1000; then according to our code,
Y1 = 1000 (-8 not 8, because Y1 is 4 bits only).
The statement sum = - sum adjusts the answer.*/
begin
Z = - Z;
end
end
could you please provide the same code for 6 bit
ReplyDelete