Thursday, 29 May 2014

verilog code for Booth Multiplier

Refer to "HDL progamming using Verilog and Vhdl " by botros for booth multiplier logic.
or watch this video




CODE:

module booth (X, Y, Z,en);
       input signed [15:0] X, Y;
 input en;
       output signed [31:0] Z;
       reg signed [31:0] Z;
       reg [1:0] temp;
       integer i;
       reg E1;
       reg [15:0] Y1;
       always @ (X, Y,en)
       begin
       Z = 32'd0;
       E1 = 1'd0;
       for (i = 0; i < 16; i = i + 1)
       begin
       temp = {X[i], E1};
     
           //The above statement is catenation
     
       Y1 = - Y;
     
           //Y1 is the 2’ complement of Y
     
       case (temp)
       2'd2 : Z [31 : 15] = Z [31 : 15] + Y1;
       2'd1 : Z [31 : 15] = Z [31 : 15] + Y;
       default : begin end
       endcase
       Z = Z >> 1;
       /*The above statement is a logical shift of one position to
           the right*/
     
       Z[31] = Z[30];
       /*The above two statements perform arithmetic shift where
       the sign of the number is preserved after the shift. */
     
       E1 = X[i];
           end
       if (Y == 16'd32)
     
       /*If Y = 1000; then according to our code,
       Y1 = 1000 (-8 not 8, because Y1 is 4 bits only).
       The statement sum = - sum adjusts the answer.*/
     
           begin
               Z = - Z;
           end
     
       end
     
       endmodule




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24 comments:

  1. output is not coming correctly.
    I gave inputs: X = 16'b0000000000000100;
    Y = 16'b0000000000000011;
    en = 1;

    Expected output is Z=00000000000000000000000000001100.

    However, obtained output is 00000000000000100000000000000110

    Can you explain how.

    ReplyDelete
    Replies
    1. you do in table form then you will obtain the same output

      Delete
  2. wrong result..not synthesizable

    ReplyDelete
  3. please provide the testbench of this code

    ReplyDelete
    Replies
    1. http://verilog-code.blogspot.com/2018/08/books-to-buy-for-beginners-verilogvhdl.html

      Delete
  4. This comment has been removed by the author.

    ReplyDelete
  5. This would give the correct answer

    module boothmul(X, Y, Z,en);
    input signed [15:0] X, Y;
    input en;
    output signed [31:0] Z;
    reg signed [31:0] Z;
    reg [1:0] temp;
    integer i;
    reg E1;
    reg [15:0] Y1;
    always @ (X, Y,en)
    begin
    Z = 32'd0;
    E1 = 1'd0;
    Y1 = - Y;
    Z[15:0]=X;
    for (i = 0; i < 16; i = i + 1)
    begin
    temp = {X[i], E1};
    case (temp)
    2'd2 : Z [31 : 16] = Z [31 : 16] + Y1;
    2'd1 : Z [31 : 16] = Z [31 : 16] + Y;
    default : begin end
    endcase
    Z = Z >> 1;
    Z[31] = Z[30];
    E1 = X[i];
    end

    end
    endmodule

    ReplyDelete
    Replies
    1. can you pls give me test bemch for this

      Delete
    2. It does not.
      Consider 2bit input : 11 * 11 (answer should be 1001) with the above code we get 0001

      Delete
  6. What does this mean?- temp = {X[i], E1}

    ReplyDelete
    Replies
    1. IT IS CONCATINATION
      http://verilog-code.blogspot.com/2018/08/books-to-buy-for-beginners-verilogvhdl.html

      Delete
  7. That is concating the Q0 and Q(-1) for performing the algorithm

    ReplyDelete
  8. please provide 32 bit and 64 bit also

    ReplyDelete
    Replies
    1. http://verilog-code.blogspot.com/2018/08/books-to-buy-for-beginners-verilogvhdl.html

      Delete
  9. plz provide the radix8 booth multiplier in vhdl1

    ReplyDelete
    Replies
    1. you got any code for radix 8 please reply

      Delete
  10. Plz provide the verilog code for 8 bit using modified booth's algorithm

    ReplyDelete
  11. how to write verilog code for vedic multiplier in sequential mode?

    ReplyDelete
  12. Could u please post test bench

    ReplyDelete
  13. at the end you did this.... i didn't get it what is the purpose of this part and what is going on this part

    if (Y == 16'd32)

    /*If Y = 1000; then according to our code,
    Y1 = 1000 (-8 not 8, because Y1 is 4 bits only).
    The statement sum = - sum adjusts the answer.*/

    begin
    Z = - Z;
    end

    end

    ReplyDelete
  14. could you please provide the same code for 6 bit

    ReplyDelete