Generate statement in verilog comes in handy when we have to instantiate a sub circuit multiple times. Consider for example you have a 32 bit adder which has 32 full adder circuits and we have to call the FA module 32 times to design a 32 bit adder. This is where the "generat" statement will be of great help. Here we will try to design a 32 bit adder using full adders and by using generate statement try to instantiate this module 32 times as per our design.
If we need a variable in our design in order to hold temporary values we have "genvar" key word for declaration.
given below is the code for 32 bit adder using generate statement:
Code:
Test fixture:
Simulation results:
RTL
Once you have simulated the code and synthesied it. Eloborate the RTL by double clicking on the FA module and you can notice that there will be exactly 32 FA module generated.
Hello guys , i have recently worked on vedic multipliers and have referred few papers too to implement it. I want to make this project open to everyone so that you can build your own Vedic multipliers and compare the results.Previously i have written about 2x2 bit Vedic multipliers which you can refer back again. We will start by designing a 2x2 multipliers and will develop a 16x16 multipliers. Once we are done with this we will proceed to build a MAC unit. A complete module which has 16x16 multiplier/MAC/ADD-SUB will be our end design
2X2 multiplier:
Design:
Figure illustrates the steps to to multiply two 2 bit numbers (design detail). Converting the above figure to a hardware equivalent we have 3 and gates which will act as 2 bit multipliers and two half adders to add the products to get the final product. Here is the hardware detail of the multiplier
Where "a" and "b" are two numbers to be multiplied and "q" is the product. With this design we are now ready to code this in verilog easily using and gates and HA(half adders). To make the design more modular we try to write code for HA first and then instantiate it to have the final product.
Code:
4X4 multiplier:
Design:
Using 4 such 2x2 multipliers and 3 adders we can built 4x4 bit multipliers as shown in the design. Proper instantiating of the 2x2 multipliers and adders. We have to first write code for 4bit and 6 bit adders. Its your choice to choose your adders. If in case you want to have better performance you can replace these normal adders with CSA or compressors. For a simpler design we have used the "+" operator which is supported by the XST synthesis tool which by default selects a low hardware adder. This architecture follows wallace tree which reduces the addition levels from 3 to just 2 stages as shown. Arrangement of the adders and the addition is explained from the figure shown below:
similar to the previous design of 4x4 multiplier , we need 4 such 4x4 multipliers to develop 8x8 multipliers. Here we need to first design 8bit and 12 bit adders and by proper instantiating of the module and connections as shown in the figure we have designed a 8x8 bit multiplier. At this point of time its necessary for you to even verify the RTL code and check if the hardware is as per your design. PlanAhead tool by xilinx gives better view of the hardware design with design elaborate option(will explain this in my next posts). Refer the addition tree diagram to know the process for 8x8 multiplier:
Code: 16x16 multiplier: Design:
Follow the same steps as in case of previous multipliers and develop 16x16 multipliers. Refer the adder tree diagram below :
code:
Here is the test bench for 16x16 vedic multipliers :
Simulation results:
RTL:
MAC design: TO being with MAC design we have to first design a accumulator which adds two number . One of which is the output of the previous stage and the other is the output from the multiplier module. Figure below shows the implementation design for mac.
It can be seen from the block diagram that the accumulator module has one input( we have designed this module be be synchronous so we have used Clock as second input). Few more control signals are required to clear(clr) the ACC unit and enable signal(en) to initiate the process of accumulation. We replace the MUL unit shown in the diagram above with out 16x16 multiplier module. Here is the code for MAC unit
code:
Simulation results :
This module cane be further devloped to convert the top module into ALU by designing your own adder/substractor and making this as the top module. please let me know if there is anything you did not understand. We are happy to help. Thank you.
Note: Replace the modules with name "add_N_bit" with a N bit adder. You can use your own adder in place of this module like csa/cla etc. If speed is not of major concern for your design use the "+" operator to create the adder modules.
Abstraction is VLSI could be defined as the amount the information an entity is hiding within it. Consider a simple analogy of the universe. We can say that universe is huge(more hidden information) , It has planets and one of which is our earth (some details are revealed ), Earth is the 5th largest planet( more details )..... I hope you get the logic. The more detailed it is , the less information it is hiding and hence we may say that it is at the low level of abstraction. The more information it hides , higher is the abstraction level. Let us just get to VLSI now from planets :-) Consider you computer for example(system) , its at a higher level of abstraction, at the next level we have boards(mother board,cd drive,disks,etc) , next we have chip level( cpu etc), inside those chips (Now we are talking about VLSI abstraction) we have four levels of abstraction namely:
Register level
Gate level(logic gates, mux, decoder etc)
circuit level (transistor)
layout level (geometry )
The figure explains the abstraction level in the deceasing order :
Designs can be expressed / viewed in one of three possible domains
Behavioral Domain (Behavioral View- using boolean expressions )
Structural/Component Domain (Structural View-connection of modules).
Physical Domain (Physical View-layout).
A design modeled in a given domain can be represented at several levels of abstraction (Details). A circuit can be represented in three level as shown in the figure below
A designer can view in either behavior level or structural level of physical level. Lets say we have a half adder design wherein we need a "and" gate and a "xor" gate. We first design these gates using behavioral description. once the gates are defined HA can be designed by instantiating the gates to give out sum and carry output for the adder. At the physical level each gate is described with its exact dimensions (layout) with its connection with other gates.
Figure below shows the abstractions ans corresponding views
Now let us try and make a simpler study about the different level of abstraction and the design views. Figure below will help you understand it better
System level:
Behavioral : Its s written specification about the end product with focus on only the end functions ,power consumption, area
Structural: Modules required for design is identified
Physical: Physical partitioning, board size is defined
Chip level:
Behavioral : behavior is explained using graphical charts and sometimes algorithms
Structural: Chips in the design and their connection is shown
Physical: size of pcb, etc, clusters(strongly connected components )
Register level:
Behavioral : Data flow from the i/p port to the o/p port using registers and combinational blocks
Structural: Components like ALU,MUX etc and their connection is shown
Physical: Floor planning , standard cell
Gate level:
Behavioral : Equation are used to define a function
Physical: Module and cell plan
Structural: Components are gates like and ,or , nand etc and their connection is show
Transistor level:
Behavioral : Tx element equation
Structural: components are transistor , resistors , capacitors etc
Physical: Mask geometry
Daniel Gajski and Robert Kuhn developed a model called the "Y" model in 1983 which was refined by Donald Thomas it in 1985. Along the tree axis of this model are the 3 abstraction level with the design view in each level as shown in the figure below.
A designer can start with one perspective and may later switch to other in the chart. There is no hard rule to stick to one view on the "Y" model.
Points to remember :
Behavior: This domain describes the temporal and functional behavior of a system.
Structure: A system is assembled from subsystems. Here the different subsystems and their interconnection to each other is contemplated for each level of abstraction.
Geometry: Important in this domain are the geometric properties of the system and its subsystems. So there is information about the size, the shape and the physical placement. Here are the restrictions about what can be implemented e. g. in respect of the length of connections.
Architectural:A system’s requirements and its basic concepts for meeting the requirements are specified here.
Algorithmic:The “how” aspect of a solution is refined. Functional descriptions about how the different subsystems interact, etc. are included.
Functional block or register-transfer:Detailed descriptions of what is going on, from what register over which line to where a data is transferred, is the contents of this level.
Logic: The single logic cell is in the focus here, but not limited to AND, OR gates, also Flip-Flops and the interconnections are specified.
Circuit: This is the actual hardware level. The transistor with its electric characteristics is used to describe the system. Information from this level printed on silicon results in the chip.
