Hello friends after a long gap i am writing a new post as i was keeping busy with some other work.
I received about 12 mails asking for Verilog code to find square root of a number so thought of writing is small post to find sqrt of a number
Here we will use the IP core from the Xilinx tool box and hoping that this module is just a part of your design and not the main project.
Create a new Verilog module and name is as " sqrt" or any another name which will help you identify the module easily.
Follow these steps
Now the next step is to paste the IP core instance to connect your main module ports to the IP core. you can get the IP instance as a file with extension as .VEO file. This instance can also be generated without the need to find the file with .veo extension. Just go the implementation mode from simulation mode and click on the IP core . In the process window you will find the instance code as shown below . Copy the instance and paste is immediately after the main code
After completing this process your final code must look like this :
//
module sqrt(
x_in,
x_out,
clk
);
input [15:0]x_in;
output [8:0]x_out;
input clk;
//instance copied now
sqare_root YourInstanceName (
.x_in(x_in), // input [15 : 0] x_in
.x_out(x_out), // ouput [8 : 0] x_out
.clk(clk)); // input clk
endmodule
I received about 12 mails asking for Verilog code to find square root of a number so thought of writing is small post to find sqrt of a number
Here we will use the IP core from the Xilinx tool box and hoping that this module is just a part of your design and not the main project.
Create a new Verilog module and name is as " sqrt" or any another name which will help you identify the module easily.
Follow these steps
- create a new Verilog project
- Right click on the module created and click on new New Source
- select the IP (core generator and architecture wizard) > give a name to the core ex. sqrt
- Go to Math Function >Square Root>Cordic 4.0 select the core and click next
- select the Square Root option and set the pipe lining mode to maximum and click next.
- select data format > unsigned integer(u can use floating if you require floating point sqrt).
- set round mode to truncate, this will give you the nearest square root of the number and click next.
- click on generate.
After completing the IP core generation process declare the i/p and o/p ports in your main module or u can just copy paste this piece of code :
// copy from here
module sqrt(
x_in,
x_out,
clk
);
input [15:0]x_in;
output [8:0]x_out;
input clk;
// PASTE YOUR INSTANCE OF IP CORE HERE
endmodule
// end of copy
Now the next step is to paste the IP core instance to connect your main module ports to the IP core. you can get the IP instance as a file with extension as .VEO file. This instance can also be generated without the need to find the file with .veo extension. Just go the implementation mode from simulation mode and click on the IP core . In the process window you will find the instance code as shown below . Copy the instance and paste is immediately after the main code
After completing this process your final code must look like this :
//
module sqrt(
x_in,
x_out,
clk
);
input [15:0]x_in;
output [8:0]x_out;
input clk;
//instance copied now
sqare_root YourInstanceName (
.x_in(x_in), // input [15 : 0] x_in
.x_out(x_out), // ouput [8 : 0] x_out
.clk(clk)); // input clk
endmodule
//
Well you are done. We are left with only the function verification which we can do with simulation,
Try testing your module with different value and check if its working fine .
Here is the simulation results which i have got for few values and the IP works perfectly fine
You can try with i/p which do not produce the perfect whole number and you may notice that the IP truncates the square root to nearest number .
I hope you will like the post , though it was quite brief :p . do let me know if there is anything you did not understand .
have a great day :-)
Also have a look at this new course :
thanks a lot :)
ReplyDeleteI simulate this design as you said. but I have 17nsec delay. I simulated this without constrain. what is that delay?
ReplyDeleteelaborate on the problem plz. wat delay are u talking of? if its combinational delay than its does not effect the simulation as every combinational ckt has its own delay. if u are facing problems simulating the code than plz follow the steps mentioned in the post u will surely get the required results :-)
Deleteif u need any further assistance on this u can mail me the snapshot of the problem with details of the problem to
sgatesrobo@gmail.com
need a verilog code for finding tan inverse or arctan for a 8bit complex number.
ReplyDeletesend the related papers to verilogblog@gmail.com. will get back on this
DeleteHi, I am new to verilog and i tried implementing this. But i am getting zeros for x_out values. In test bench I have given x_in as 16'd9 and clk as 1. Please tell me if i am doing anything wrong.
ReplyDeleteAlso, please elaborate on how to get results as you have shown, like different inputs and their outputs in decimal format. I am getting everything in binary. Thanks.
hai....can you please tell me how do I implement a sinh function using cordic core...in which form will I get the output in isim simulator??
ReplyDeletehow to find a middle value in a squared number sequence of a sorted array using verilog code
ReplyDelete