Showing posts with label FIR FILTER VERILOG CODE. Show all posts
Showing posts with label FIR FILTER VERILOG CODE. Show all posts

Friday, 6 September 2013

FIR FILTER DESIGN USING VERILOG








     FIR filters are is widely used in different applications such as biomedical, communication and control due to its easily implementation, stability and best performance. Its simplicity makes it attractive for many applications where it is need to minimize computational requirements.


Filters play an important role for removal of unwanted signal or noise from original input signal by removing the selected frequencies from incoming signal. They became much popular due to the increase of the digital signal processing.

 Comparison between FIR and IIR Filters

The non recursive (FIR) and recursive (IIR) filters have different characteristics for numbers of applications. The non recursive filters are chosen due to its best performance of numerical operations, differentiation and integration. The table 2.1 below shows the comparison between FIR and IIR filters.


IIR
FIR
More Efficient

Less Efficient
Analog Equivalent

No Analog Equivalent

May Be Unstable

Always Stable
Non-Linear Phase Response

Linear Phase Response

No Efficiency Gained by Decimation
Decimation Increases Efficiency





VERILOG CODE FOR FIR FILTER
// main module FIR
module filterfir(clk,rst,x,dataout);
input [7:0]x;
input clk,rst;
output [9:0]dataout;
wire [7:0]d1,d2,d3;
wire [7:0]m1,m2,m3,m4,m5;
wire [7:0]d11,d12,d13,d14;
parameter h0=3'b101;
parameter h1=3'b100;
parameter h2=3'b011;
parameter h3=3'b010;
parameter h4=3'b001;
assign m1=x>>h0;
dff u2(clk,rst,x,d11);
assign m2=d11>>h1;
assign d1=m1+m2;
dff u4(clk,rst,d11,d12);
assign m3=d12>>h2;
assign d2=d1+m3;
dff u6(clk,rst,d12,d13);
assign m4=d13>>h3;
assign d3=d2+m4;
dff u8(clk,rst,d13,d14);
assign m5=d14>>h4;
assign dataout=d3+m5;
endmodule

module dff(clk,rst,d,q);// sub module d flipflop
input clk,rst;
input [7:0]d;
output [7:0]q;
reg [7:0]q;
always@(posedge clk)
begin
if(rst==1)
begin
q=0;
end
else
begin
q=d;
end
end

endmodule


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