Link for the coupons : Here
Generate statement in verilog comes in handy when we have to instantiate a sub circuit multiple times. Consider for example you have a 32 bit adder which has 32 full adder circuits and we have to call the FA module 32 times to design a 32 bit adder. This is where the "generat" statement will be of great help. Here we will try to design a 32 bit adder using full adders and by using generate statement try to instantiate this module 32 times as per our design.
If we need a variable in our design in order to hold temporary values we have "genvar" key word for declaration.
given below is the code for 32 bit adder using generate statement:
Code:
Test fixture:
Simulation results:
RTL
Once you have simulated the code and synthesied it. Eloborate the RTL by double clicking on the FA module and you can notice that there will be exactly 32 FA module generated.
module vedic2by2(a,b,c);
ReplyDeleteinput [1:0]a;
input [1:0]b;
output [3:0]c;
wire [3:0]c;
wire [3:0]temp;
//stage 1
// four multiplication operation of bits accourding to vedic logic done using and gates
assign c[0]=a[0]&b[0];
assign temp[0]=a[1]&b[0];
assign temp[1]=a[0]&b[1];
assign temp[2]=a[1]&b[1];
//stage two
// using two half adders
ha zp1(temp[0],temp[1],c[1],temp[3]);
ha zp2(temp[2],temp[3],c[2],c[3]);
endmodule
module ha(a1,b1,c1,s1);
input a1,b1;
output s1,c1;
assign s1=a1^b1;
assign c1=a1&b1;
endmodule
//by charantej.peteti@gmail.com
http://verilog-code.blogspot.com/2018/08/books-to-buy-for-beginners-verilogvhdl.html
Delete