Linear Feed Back Shift Registers Using Verilog

Hie ,Here is yet another post about VLSI testing. In the last post we discussed about the testing of sequential circuits with the help of Scan Cells. Lets assume if we had the input bits to be some 100 bits long . In such a situation its again a nightmare to manually enter the inputs to the circuit under test and which is not practical too. Various test patterns generators have been proposed to trigger the inputs to the Circuit Under Test(CUT) which will produce random patterns for every clock cycle and reduces the burden to manually insert these as inputs to the CUT.    Figure below Shows the general scheme to test any circuit

       

     The Control Unit is responsible to coordinate the operation of the testing circuit.When the MUX select signal is HIGH (1) The circuit is said to be in the TEST mode or else its in the normal mode.Under Test mode the input to the CUT is from the Test Pattern Generator which will apply the test vectors to the CUT to be tested. The output response of the CUT are compared with the fault free response to declare the CUT as fault or fault free. In this post we will discuss about the Test Generators(TG) and the remaining blocks will be explained in my next post. 

      The choice of TG is an important criteria to ensure high fault coverage for the CUT and to make sure the circuit is working or not. Pattern generators like LFSR(Linear Feed Back Shift Registers ) can produce random patterns with low hardware requirements and is preferred choice for testing. It is categorized under pseudo-random test pattern generators which can produce a random pattern for every clock cycle applied to it. The figure below shows the general structure for a LFSR

 

     It consist of D-FF connected in cascade as shown with the same clock applied to all the FF to make them act like a shift register. But the only change is that the input to the first (D3 in th figure) is from the XOR of the o/p from FF's 0 and 3 (from fig). This XOR operation introduces a new  bit into the shift register .When we take out the output of these FF they will have a random pattern. This is a general structure for a 4 bit LFSR. The inputs to the XOR are called the Taps. So from the figure above the Taps are 0 and 3 FF's. There is no such order from where the inputs to the XOR comes from to produce a random pattern. But the pattern has to be of maximum length . By maximum length we mean that the pattern must repeat itself after 2^N clock cycles for a N bit LFSR. In our example if the LFSR has to be of maximum length then the pattern has to repeat after 16(2^4) clock cycles. For a small LFSR like the present one (4bit) its easy to identify the Taps to the XOR gate which can produce maximum length output but just imagine how can we identify the Taps for the XOR if the number of bits is 10bits ? Obviously we cant go by BRUTE FORCE method by trying all possible combination to identify the Taps which will produce maximum length sequence. Figure below shows the maximum length sequence produced by a 4 bit LFSR.

   

     You can notice that after 16 cycles the pattern is repeating for the LFSR. The Tap identification is the major criteria to produce a sequence like this which will repeat after 2^N clock cycles.But the fact is that the inputs for a CUT cannot be practically more than 128 bits or so. Xilinx has documented the Taps to be given for a given LFSR up to 165 bits. This makes the task for coding for LFSR by just using DFF and XOR gates with the Taps given by the Xilinx documentation. With these basics we can now proceed to design a LFSR for TG used in testing.

Design :

Components Required for Design : 

• D-Flip Flops
• XOR Gates

To illustrate the concept of LFSR and maximun length sequecne we will 4 bit LFSR. The Taps according to the Xilinx Document to produce a 6 bit maximum length sequence are 4 & 3(i.e the inputs to the XOR gate are from output of FF number 4 and 3). Figure below shows the RTL of the 4 bit LFSR.

                                                                        RTL

   
    You can notice that the inputs to the XOR gate are from o/p for DFF 4 and 3 and the output of this XOR gate is fed as input to the first FF. Figure below shows the simulation results of 4 bit LFSR which produces random patterns and which repeats exactly after 16 clock cyles.

                                                                 SIMULATION 

                                                           

CODE

module lfsr_N_1(
d,
q,
rst,
clk
    );
parameter N=3;//given N one less than the number of FF in your design
input clk;
input d;
input rst;
output [0:N]q;
reg [0:N]q;

always@(posedge clk)
begin
 if(rst && d)
q<=1'b1;
else
4'b011:q={q[N]^q[N-1],q[0:N-1]};    //change the taps here for your design
end
endmodule


Advantages:

• Low hardware 
• Maximum length sequence can be produced 
• Used for BIST

If you want to code for a N bit LFSR where N can be any number from 3 to 165 all you need to do is to declare a parameter N and write you code for the LFSR with Taps from the Xilinx Document. The links to the Xilinx Document and the references are given below

References:

• Paper used 
• Xilinx Documentaion

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Note: The code above works for only 4 bit, To make it work for any given N bit just change the Tap inputs. And the memory format used for coding is big endian format and you make change it to little endian format