Carry select Adder using Verilog

                                                           RTL SCHEMATIC





















                                                 

SIMULATION RESULTS

                                                                   CODE



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BLOCK DIAGRAM FOR IMPLEMENTATION 

Advantages : 

• No need to wait for carry in every stage
• Once the carry is known immediately the result can be obtained
• Low delay of just 3 Ripple Carry Adders

I have been getting lot of mail & requests to provide the test bench also for CSA. Here is the Test feature module for CSA for you :


module test_csa;

// Inputs
reg [3:0] a;
reg [3:0] b;
reg cin;

// Outputs
wire [3:0] sum;
wire co;

// Instantiate the Unit Under Test (UUT)
carry_select uut (
.a(a), 
.b(b), 
.cin(cin), 
.sum(sum), 
.co(co)
);

initial begin
// Initialize Inputs
a = 0;
b = 0;
cin = 0;
#100;

a = 4'd5;
b = 4'd10;
cin = 0;
#100;

a = 4'd5;
b = 4'd10;
cin = 1;
#100;


a = 4'd15;
b = 4'd10;
cin = 0;
#100;


a = 4'd15;
b = 4'd11;
cin = 1;
#100;


// Add stimulus here

end

endmodule

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