RTL Schematic/Technology schematic

RTL Code:

Hello there. I have been posting about the Verilog coding since a month & just to add to it will deal with the RTL coding today for your design. :)  This post is to completely understand and analyze the RTL code which includes the RTL schematic and the Technology schematic. Having completed your Verilog coding the next step which you all know is to simulate it and verify if the design is working fine. Up to this point in the flow of design process we are still in the software part of coding. To view the code in terms of hardware you will have to move a step ahead and go for “Synthesis “ .  To put it in simple terms synthesis implies the hardware equivalent of your written Verilog code. There are inbuilt synthesis tool which are part of Xilinx & the one which is used is the XST tool. The job of the synthesis tool is to read the code written in Verilog/hdl and with the aid of the library files it has to convert this code to a hardware description netlist. The figure below shows how the process works.

 

Xst tool is quite user friendly to use & it produces the synthesized design just by a few clicks. But one thing is always true, the easier it looks the more complex program is running behind. J we will start now with the Xilinx RTL coding by considering a simple code(D flip flop) and lets try to create both the technology schematic and RTL schematic for it. The Verilog code for D flip flop is given below

module dff(d,clk,rst,en,q,qbar

    );

input d;

input clk;

input rst; // reset

input en; //enable

output q;

output qbar;

reg q;

wire qbar;

assign qbar=!q;

always @(posedge clk)

begin

if(rst) //if reset is high make q=0

q=0;

else if(en)

begin // if reset is low and en is high make ff transparent

q=d;

end

end

endmodule

The objective is not to analyze the code now but to check how the code is mapped to hardware. You can copy this code from here & work in parallel as I take you through the RTL coding. Okie , now change the mode of Xilinx from simulation to implementation mode.  You will find the Synthesis XST option on the right side as show. 

In the Processes pane, right-click Synthesize - XST, and select Process Properties to open the Synthesis

 Options dialog box. Set the Keep Hierarchy option to Yes as shown. 

This is to ensurethat we have the flexibility of viewing the hardware for every module is our design(in case you have many modules in your design). Now just double click on the “View RTL schematic” & you will get a pop up window like this one

Just say OK and the next window will pop up. Select the hierarchical block named dff, and move it to Selected Elements using the Add button, and then click Create Schematic. we are done J the RTL for our code is now generated. It must look like this one

Well now comes the interesting part. J the figure shows the internal and external signals. The border here for this block has a triangle at each edge which indicates that this block is not a primitive but part of our hierarchical design. if you double click on this you will get the exact hardware equivalent of the code . it has a block named “fdre” which is a D flip flop from the library about which we talked about earlier and a "not" gate is present along with it .

   

Now if you place the mouse cursor on any of these elements or the signals the details are displayed. Try it for yourself. For example if you place the cursor on the “fdre” is will display “BLOCK=q,Type=fdre,INT=0”. If you try the same with the signal it will display the number of pins connected to that particular signals. We are now dealing with a simple design (dff)so there are no pins that are invisible. If you try with a complex design you will discover that few pins will be mentioned invisible.

Instead of placing the cursor if you click on a signal you find two symbols indicating the start and end point of the signal.

The RTL schematic generated by the XST tool will be saved in the “.ngr” file format and this schematic is independent of the target device where you want to test your design, in our case its Spartan-3 fpga). If you want to view the exact hardware as it will be mapped to your target FPGA device you will have to go for “view Technology schematic and repeat the same process.

The file format for technology schematic is “.ngc”. Here is how your technology schematic will look like & notice that this one is different from the RTL schematic.

Clearly the input signals are first saved using buffers as it can be noticed. This is necessary because in real time implementation it will be necessary to save the inputs in buffers and then propagate them to the internal design. This avoids the synchronization problems between the FPGA and the inputs devices. 

 Well I hope this post was useful to you, if so do write back to me 

BYE :) 

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EXPLORING THE SCHEMATIC VIEWER WINDOW

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 The schematic Viewer window is given here with reference to the each icon present to assist you to speed up your RTL coding skills :

1. The schematic window is the main window where you explore your design by adding or removing elements.

2. This toolbar contains the functions specific to the Schematic Viewer.

3. This panel contains two types of information: objects visible on the schematic (instances, pins and signals) and object properties. For example, you can select a BRAM primitive in your schematic and see all its properties, including BRAM initialization values.

Note: You must select the View by Category tab to see this panel.

4. This toolbar contains functions shared by different graphical tools such as Zoom

Zoom options :