Vedic
Multipliers:
You
all must have heard of Vedic mathematics and I am sure you must have tried few Vedic
logic to add/multiply/divide etc.. What is more interesting about Vedic is the
logic behind it. Ever since it has come into existence people have tried coming
up with their own set of Vedic hardware keeping the low power issues and the
area constraints. I came across one such logic using Vedic maths for fast
multiplications and browsed few papers related to it. Interestingly I noticed
that its quite simple for anyone to design their own Vedic hardware multiplier
using Verilog. So I tried doing it myself using few papers and resources. Guess
what? it worked
The
Vedic logic I used is the “Urdhva Triyakbhyam Sutra” . If you google it I am
sure u will get the logic so i will not explain much about logic here but
instead will start with the hardware design of Vedic multiplier. Here is
snapshot of the logic which is easy to understand
The
figure shows how to multiply two 2 bit numbers using Urdhva Triyakbhyam Sutra. Now with this logic we have to convert it
to a equivalent hardware. Two bit multiplication is equivalent to a “and” gate so my first part is over. Next part is to add two bits which is nothing but a
half adder and for our logic we need two half adders. U can easily code for a
half adder, If not its available here http://verilog-code.blogspot.in/p/verilog-codesprojects.html
. Let’s start
with the coding now and make sure that you have understood the logic well
before you proceed reading .
To start with the design
has two stages:
1> Multiplier stage
using “and” gates and we need four such gates
2> half adders and two
such adders
[Note: the carry of first
adder must be added to the second adder]
This is my black box model
showing only the inputs and outputs:
showing only the inputs and outputs:
hie
ReplyDeletesuper le somya...doing good work le......ur code is working fine...put verilog code for 16 bit vedic multiplier.........as soon as possible ..with test bench.........
ReplyDeletePlease mail your request to sgatesrobo@gmail.com -Verilog team
Deletecan you put verilog code for 32bit Vedic multiplier
Deletesir can you post the verilog code for ALU based on vedic maths(addition and subtraction)
ReplyDeletehttp://verilog-code.blogspot.in/2014/01/design-and-implementation-of-16-bit.html
DeleteYou can go through this post where i have implemented a vedic mac.
i need verilog code of 16-bits of vedic multiplier ... as soon as possible ..
ReplyDeletehai.. i used vedicmultiplier concept in my mtech project i published paper aso in IJERT june 2013 volume 2(double precison Floating point MAC )
ReplyDeletei did simulation (verilog coding) work to prove vedic work good compare to others multiplier with convolution as an example. if any body vng interest in analog design for this i can help u out (mail me: dhanu.phoniex@gmail.com)
all blocks in this module are digital. what do you mean by analog design?
DeleteHi...can u send me the verilog code for 16-bit nikhilam vedic multiplier
ReplyDeletemail id:-eswar.gantasala@gmail.com
i need verilog code of 16-bits of vedic multiplier.....ASAP...
ReplyDeletemy email id: rajputrocks10091993@gmail.com
how can we develop a signed vedic multiplier
ReplyDeleteyou will have to re-design the multiplier for signed numbers. use the msb bit for sign representation and other bits for data..
Deletei need verilog code of 32-bits of vedic multiplier.....ASAP...
ReplyDeletemy email id: vishalemshaddy@gmail.com
Plz mail me 16 bit vedic multiplier code druvakumar12@gmail.com
ReplyDeletePlz mail me 16 bit vedic multiplier code druvakumar12@gmail.com
ReplyDeleteplease mail me 16 bit multiplier code mailabhinaykumar@gmail.com
ReplyDeleteplease reply.....
module MUL16X16(
ReplyDeletea,
b,
c
);
input [15:0]a;
input [15:0]b;
output [31:0]c;
wire [15:0]q0;
wire [15:0]q1;
wire [15:0]q2;
wire [15:0]q3;
wire [31:0]c;
wire [15:0]temp1;
wire [23:0]temp2;
wire [23:0]temp3;
wire [23:0]temp4;
wire [15:0]q4;
wire [23:0]q5;
wire [23:0]q6;
// using 4 8x8 multipliers
MUL8X8 z1(a[7:0],b[7:0],q0[15:0]);
MUL8X8 z2(a[15:8],b[7:0],q1[15:0]);
MUL8X8 z3(a[7:0],b[15:8],q2[15:0]);
MUL8X8 z4(a[15:8],b[15:8],q3[15:0]);
// stage 1 adders
assign temp1 ={8'b0,q0[15:8]};
N_BITADDER_16 z5(q1[15:0],temp1,q4);
assign temp2 ={8'b0,q2[15:0]};
assign temp3 ={q3[15:0],8'b0};
N_BITADDER_24 z6(temp2,temp3,q5);
assign temp4={8'b0,q4[15:0]};
//stage 2 adder
N_BITADDER_24 z7(temp4,q5,q6);
// fnal output assignment
assign c[7:0]=q0[7:0];
assign c[31:8]=q6[23:0];
endmodule
Will please send me 64bit vedic multiplier using mac unit
Deletecode is already on the blog . just follow the syntax and use it for any number of bits
ReplyDeleteplz send 16 bit code for vedic multiplier using yavadanum formula
ReplyDeleteI need 64 bit Verilog multiplier code
ReplyDeletemy mail id chedevineeth123sai@gmail.com plz its urgent
ReplyDeleteHello Sir I want to replace the normal adders with the Carry Select Adders so what changes should be done in the above code
ReplyDelete