Verilog code for Interpolation filter with factor 2

Link for the coupons : Here

Interpolation filter Design using Verilog Code.

interpolation factor = 2
coefficient number =10 ={1,0,0,0,0,0,0,0,0,0}
input sequence seq_in = {1,2,3,4,5,6,7,8,9....}
output sequence seq_out ={1,0,2,0,3,0,4,0,5,0,6....}
the below code helps us to get the interpolated sequence using interpolation factor 2
it uses the state machine and it is active low reset
every 10th clock the output is generated

//---------------function_multi.v------------------multiplication_function-------------------//

//---------------------used the function for multiplication---------------------------------//

module multiplication (input1 ,input2,output,clk,rst);

parameter WIDTH_IN=12                         ;

parameter WIDTH_OUT=20                        ;

input       [WIDTH_IN-1:0]input1              ;

input       [WIDTH_IN-1:0]input2              ;

input       clk,rst                           ;

output       [WIDTH_OUT-1:0]output            ;

always@(posedge clk)

begin 

if(!rst)

ouput<=0                                      ;

else

output<=input1*input2                       ;

end 

endmodule

//-------------------------------------------------------------------------------------------//

//-------------------------------------------------------------------------------------------//

//--------------------------------interpolTION-----------------------------------------------// 

 `include "function_multi.v"                       //multiplication function

//-----------------------------------------------------------------------------//

module interpolation(

         seq_in                           ,//input sequence

         seq_out                          ,//interpolated output sequence

         rst                              ,//reset

         clk                               //system clock

); 

//-----------------------------------parameter------------------------------------------------//

parameter WIDTH_IN=12                       ;//input width

parameter WIDTH_OUT=18                      ;//output width

//----------------------------------COEFFICENTs-----------------------------------------------//

parameter signed H1= 1                      ;//coefficents from h1 to h10

parameter signed H2= 0                      ;

parameter signed H3= 0                      ;

parameter signed H4= 0                      ;

parameter signed H5= 0                      ;

parameter signed H6= 0                      ;

parameter signed H7= 0                      ;

parameter signed H8= 0                      ;

parameter signed H9= 0                      ;

parameter signed H10=0                      ;

//-----------------------------------------REGISTER-------------------------------------------//

reg signed  [WIDTH_IN-1:0] q1, q2, q3, q4, q5, q6, q7, q8, q9,q10            ;//shift registers 

reg signed [WIDTH_OUT-1:0]accum1            ;//accumulator for 1st clock of operation

reg signed [WIDTH_OUT-1:0]accum2            ;//accumulator for 2nd clock of operation

reg signed [WIDTH_OUT-1:0]accum3            ;//accumulator for 3rd clock of operation

reg signed [WIDTH_OUT-1:0]accum4            ;//accumulator for 4th clock of operation

reg signed [WIDTH_OUT-1:0]accum5            ;//accumulator for 5th clock of operation

reg signed [WIDTH_OUT-1:0]accum6            ;//accumulator for 6th clock of operation

reg signed [WIDTH_OUT-1:0]accum7            ;//accumulator for 7st clock of operation

reg signed [WIDTH_OUT-1:0]accum8            ;//accumulator for 8th clock of operation

reg signed [WIDTH_OUT-1:0]accum9            ;//accumulator for9th clock of operation

reg signed [WIDTH_OUT-1:0]accum10           ;//accumulator for 10th clock of operation

reg signed [WIDTH_IN-1:0]in1m1,in2m1        ;//input to 1st multiplier

reg [11:0]out                               ;//register for ring counter

reg [3:0]state=4'b0001                      ;//state register 

//---------------------------------------wire-------------------------------------------------//

wire  [WIDTH_OUT-1:0]out_add                    ;//output from the multiplier

//----------------------------------------input------------------------------------------------//

 input signed [WIDTH_IN-1:0]seq_in               ;//input sequence 

 input clk,rst                                   ;//system clock,reset

//-----------------------------------------output---------------------------------------------//

output  reg signed [WIDTH_OUT-1:0]seq_out       ;//output sequence

//------------------------------------------logic-------------------------------------------//

always@(posedge clk)begin

  if(!rst)begin

    accum1<=0                               ;//reset=0,all register becomes zero

    accum2<=0                               ;

    accum3<=0                               ;

    accum4<=0                               ;

    accum5<=0                               ;

    accum6<=0                               ;

    accum7<=0                               ;

    accum8<=0                               ;

    accum9<=0                               ;

    accum10<=0                              ;

    in1m1<=0                                ;

    in1m2<=0                                ;

    q1<=8'b00000000                         ;

    q2<=8'b00000000                         ;

    q3<=8'b00000000                         ;

    q4<=8'b00000000                         ;

    q5<=8'b00000000                         ;

    q6<=8'b00000000                         ;

    q7<=8'b00000000                         ;

    q8<=8'b00000000                         ;

    q9<=8'b00000000                         ;

    q10<=8'b00000000                        ;

    end  

    else 

    q1<=seq_in                              ;               

    q2<=q1                                  ;

    q3<=q2                                  ;

    q4<=q3                                  ;

    q5<=q4                                  ;

    q6<=q5                                  ; 

    q7<=q6                                  ;

    q8<=q7                                  ;

    q9<=q8                                  ; 

    q10<=q9                                 ;

    end

//----------------------------------------------state machine---------------------------------//

always@(posedge clk)begin 

case(state)

4'b0001:begin  

        in1m1<=q1        ;

        in2m1<=H1        ;

        accum1<=out_add  ;  

        state<=4'b0010   ;

        end

4'b0010:begin

        in1m1<=q2       ;

        in2m1<=H2       ;

        accum2<=out_add ;

        state<=4'b0011  ;

        end

4'b0011:begin

       in1m1<=q3        ;

       in2m1<=H3        ;

       accum3<=out_add  ;

       state<=4'b0100   ;

       end

4'b0100:begin

       in1m1<=q4        ;

       in2m1<=H4        ;

       accum4<=out_add  ;

       state<=4'b0101   ; 

       end

4'b0101:begin

        in1m1<= q5      ;

        in2m1<=H5       ;

        accum5<=out_add ;

        state<=4'b0110  ;

        end  

4'b0110:begin

        in1m1<= q6      ;

        in2m1<=H6       ;

        accum6<=out_add ;

        state<=4'b0111  ;

        end 

4'b0111:begin 

        in1m1<=q7        ;

        in2m1<=H7        ;

        accum7<=out_add  ;  

        state<=4'b1000   ;

        end

4'b1000:begin

        in1m1<=q8       ;

        in2m1<=H8       ;

        accum8<=out_add ;

        state<=4'b1001  ;

        end 

4'b1001:begin

        in1m1<=q9        ;

        in2m1<=H9        ;

        accum9<=out_add  ;

        state<=4'b1010   ;

        end

4'b1010:begin

        in1m1<= q10      ;

        in2m1<=H10       ;

        accum10<=out_add ;

        seq_out<=(accum1+accum2+accum3+accum4+accum5+accum6+accum7_accum8+accum9+accum10);//output calculated

        state<=4'b0000   ;

        end

//-------------------------------------------multipliers--------------------------------------//

multiplication   m1(.clk(clk  ), 

                .rst(rst),

                .input1(in1m1),

                .input2(in2m1),

                .output(out_add)

    );

endmodule

Please Note : Our course is now listed for Udemy training by Industry and leading companies use our courses  :
Analog Design- Intuitive Approach
Rc Circuits Analysis With LT Spice
Basics of Mosfet - Simplified View

Please use these links or share with someone who might be interested.
Note : Author discounts are already applied to these links. 

Types of state machine (FSM) and its example in verilog

There are two types of state machine(FSM)they are listed as:

1:Mealy machine
2:Moore machine

• Mealy machine: is a FSM whose output values are determined both by its current state and the current inputs.   
• Moore machine: is a FSM whose output values are determined only by its current state only. 

    
 

Example:

1)Mealy module: sequence detector
  For the example go to the link below which is already available in our blog  
httngp://verilog-code.blogspot.in/2014/08/finite-state-machine-design-for.html


2)Moore machine: traffic light controller
    assumption made,
    This module has input clock and output color of light .
   

   output is assigned by the determining the state only, It consists of three states such as 00,01,10. it is shown in the example below.present state is set with respect to clock and output is set with respect to states hence output is not determined by input it is determined by the present state only.

 //-------------------------------------------------------------------------------------------------------------------------//


          module traffic_light( clk                                ,              
                                            light                             );
          //--------------------------------------------------------------------------------------------------//
          parameter  RED =3'b000,GREEN=3'b010 ,YELLOW = 3'b001; 

          //-------------------------------------------------------------------------------- ------------------//
          input clk                                                        ;
          output [0:2]light                                            ;

           //---------------------------------------------------------------------------------------------------//
          reg [0:1]state                                                ;
          reg [0:2]light                                                 ;
       
          //-------------------------------------------------------------------------------------------------//

          always@(posedge clk)
            begin
                   case(state)

                   2'b00: begin
                                  light<=YELLOW                 ;
                                  state<=2'b01                       ;
                              end

                   2'b01: begin
                                  light<=GREEN                    ;
                                  state<=2'b10                       ;
                              end

                   2'b10: begin
                                  light<=RED                        ;
                                  state<=2'b00                      ;
                              end
          
                   default:begin
                                  light<=RED                        ;
                                  state<=2'b00                      ;
                              end

                endcase
          end
        endmodule

           

         
                

state machine coding of counters in verilog

Link for the coupons : Here

what is a state machine?
It is a sequential circuit which has some predefined state. The system goes through these states as per the control signal.
Transition takes place for every clock and in some cases it depends on few control signals .


Applications:
State machines are important part of embedded systems. Once we know that a system has to go through a set of well defined states we can design the system and make the machine to act accordingly .



Here i m giving a flow which must be followed to design any state machine.

1. define the states from the specification given.
2. draw state diagram - this must show the states and also transition between the states.
3. decide the flip flop to be used - JK/D/T.. preferably D comes in handy but not necessary in all situations.
4. construct excitation table and get the expression of the FF in terms of its output.
5. draw the circuit diagram from the expression.
6. implement the design in verilog.

Note: number of states will  decide the number of FF to be used.
Example. for a 3 bit counter the number of states is 8. and number of FF needed is 3. i.e 2^3=8

 Let us start the design for a 3 bit even counter as an example and we will apply all the steps listed above for this specification.

1.Spec: count sequence : 0 > 2 >4 > 6 and repeat

2.State diagram















3. D -FLip Flop selected.
4. Excitation table for D-FF and expression for D0,D1 and D0

 

From  the excitation table write the K-map for D0, D1 and D2 in terms of Q2,Q1 and Q0 respectively.And get the expression of D0,D1 and D2 from the K-map

         D0=0 

                                

5. circuit diagram :

6. implement the design in verilog:

write a structural code in verilog using "asynchronous D-FF and an xor gate and make connections as shown in the circuit diagram. 

CODE:

module counter_state(clk,rst,q
    );
input clk,rst;
output  [2:0]q;
d_async d0(0,rst,clk,q[0],);
d_async d1(~q[1],rst,clk,q[1],);
d_async d2(q[2]^q[1],rst,clk,q[2],);  //d,rst,clk,q,qb
endmodule

RTL_schematic:

 

Simulation results

Please Note : Our course is now listed for Udemy training by Industry and leading companies use our courses  :

Analog Design- Intuitive Approach

Rc Circuits Analysis With LT Spice

Basics of Mosfet - Simplified View

Please use these links or share with someone who might be interested.

Note : Author discounts are already applied to these links. 

Finite State Machine Design For Sequence Detector

    FSM DESIGN MADE SIMPLE             

       Hie, its been a long time since i updated my blog as i was busy with other projects. In last one month i have received many requests to provide the more details on FSM coding so here is it for you.Today i am going to explain how to create a simple FSM using verilog with an example of sequence detector. FSM is a simple system by itself and its designed to perform certain functions. Take for example traffic light controller ,lift operation, etc.
         

                   Every FSM has fixed states through which it has to pass. For a traffic light the initial state might be "red light on" followed by "saffron on" then "green on". In every state the FSM does some operation and after its completed is moves ahead to the next state. So to design a FSM we have to first define the number states of possible states the system must have. Once number of states are identified we have to specify the task to be done in every state. The last step is to define condition for transition from one state to next. A diagram which shows all the details of FSM is called the state diagram which shows all the states and also shows the condition for transition from present to next state.

Link for the coupons : Here

     Note: every FSM must and should have a reset state. This is because there are possibilities that our system can go to an unknown state which is not defined by us. This can completely make the system remain in that state forever. To avoid such situations "reset " is used to bring back the FSM to a known state.

Steps to build FSM:

1. Identify number of states 
2. Define task to be performed in every state
3. condition for tradition from one state to next
4. Draw a state diagram for the complete system

Consider we have a FSM which must detect the number "0111" which is a sequence. For this problem statement let us try and build a FSM following the steps given above.

Number of states: 

• Reset State
• State 1- detect  "0"
• State 2- detect  "01"
• State 3- detect  "011"
• State 4- detect  "0111"

Draw a state diagram showing states and transition between states as shown below:

            Best practice to build any complex FSM is to first draw the state diagram on paper and then convert it to an equivalent verilog code. Conversion from state diagram to code is quite a simple process , most of the time must be spent in drawing the state diagram correctly rest of the job is not that complicated. Figure below shows to write a code for any FSM in general. Code fragment must look like the one shown below.

Code fragment for any FSM:

module();

//declare all inputs and outputs

-

-

//use two registers , one to hold current state and one for next state

reg [N-1:0]current_state,next_state; 

-where N is number of states.

//declare all states 

-

-

-

-

// define state and state transition here using case statement

-Here we have to mention the transition of states. for example, if the current state is "state0" and if reset if "0" then the next state has to be "state1" and at any state if reset is "1" the next state will be "reset". when FSM is in the last states it goes again back to the first states and the process repeats.

// use control signal to indicate correct results

-In our example of sequence detector when the FSM is in the "state0111" it implies that the sequence is detected so to indicate this we need a signal which will set when state is "0111". 

Conversion from state diagram to Verilog code:

`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////

// Engineer: Somshekhar R Puranmath

// Design Name:   sequence_0111

// Project Name:  sequence_counter_0111

////////////////////////////////////////////////////////////////////////////////

module sequence_0111(clock, reset, in_bit, out_bit

    );

//declare all inputs and outputs

  input clock, reset, in_bit;

  output out_bit;

  // use registers to hold current and next states

  reg [2:0] state_reg, next_state;

  // State declaration

  parameter    reset_state  =  3'b000;

  parameter    read_zero =   3'b001;

  parameter    read_0_one =   3'b010;

  parameter    read_zero_one_one = 3'b011;

  parameter    read_zero_one_one_one= 3'b100;

  

  // state register , for every clock cycle the FSM  state registers are updated

  always @ (posedge clock or posedge reset)

     if (reset == 1) 

        state_reg <= reset_state; 

     else  

        state_reg <= next_state;

  // next-state logic, transistion from current to next state

always @ (state_reg or in_bit) 

    case (state_reg)

        reset_state: 

              if (in_bit == 0) 

                  next_state = read_zero; 

              else if (in_bit == 1) 

                  next_state = reset_state;

              else next_state = reset_state;

        read_zero: 

              if (in_bit == 0) 

                  next_state = read_zero; 

              else if (in_bit == 1) 

                  next_state = read_0_one;

              else next_state = reset_state;

        read_0_one: 

              if (in_bit == 0) 

                  next_state = read_zero; 

              else if (in_bit == 1) 

                  next_state =  read_zero_one_one;

              else next_state = reset_state;

 read_zero_one_one: 

            if (in_bit == 0) 

                next_state = read_zero;

            else if (in_bit == 1) 

                next_state = read_zero_one_one_one;

            else  next_state = reset_state;

      read_zero_one_one_one: 

            if (in_bit == 0) 

                next_state = read_zero; 

            else if (in_bit == 1) 

                next_state = reset_state;

            else next_state = reset_state;

        default: next_state = reset_state;

  endcase

assign out_bit = (state_reg == read_zero_one_one_one)? 1 : 0; // control signal to indicate sequence //is detected 

endmodule

Test bench for sequence detector:

`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////

// Engineer: Somshekhar R Puranmath

// Design Name:   sequence_0111

// Project Name:  sequence_counter_0111

////////////////////////////////////////////////////////////////////////////////

module test_ma_sequence;

// Inputs

reg clock;

reg reset;

reg in_bit;

// Outputs

wire out_bit;

// Instantiate the Unit Under Test (UUT)

sequence_0111 uut (

.clock(clock), 

.reset(reset), 

.in_bit(in_bit), 

.out_bit(out_bit)

);

initial begin

// Initialize Inputs

clock = 0;

reset = 0;

in_bit = 0;

// Wait 100 ns for global reset to finish

#10;

reset = 1;

in_bit = 0;

#10;

reset = 0;

in_bit = 0;

#10;

        

 reset = 0;

in_bit = 1;

#10;

reset = 0;

in_bit = 1;

#10;

reset = 0;

in_bit = 1;

#10;

Click Here for reference Book : MUST READ BOOK

// Add stimulus here

reset = 1;

in_bit = 1;

#10;

reset = 0;

in_bit = 0;

#10;

reset = 0;

in_bit = 1;

#10;

reset = 0;

in_bit = 1;

#10;

reset = 0;

in_bit = 1;

#10;

end

 always begin #5 clock=~clock; end    

endmodule

Simulation Results:

RTL schematic:

Do write back to me for more details on FSM coding at verilogblog@gmail.com.. have a nice day

Please Note : Our course is now listed for Udemy training by Industry and leading companies use our courses  :
Analog Design- Intuitive Approach
Rc Circuits Analysis With LT Spice
Basics of Mosfet - Simplified View
Please use these links or share with someone who might be interested.
Note : Author discounts are already applied to these links. 

VHDL to VIRILOG and VERILOG to VHDL

Hello everyone,
Here is a tool which can be used to convert verilog to vhdl and vice-versa. I had tried a lot searching for a free tool online  and finally found this one which is cool to use and easy to operate. You can click on the link below and use it.

I have tried converting few simple VHDL programs to verilog and it works fine.

Here are some snapshots of one such program with steps for conversion:
step 1: run the software

step 2: Click on the tab  " VHDL TO VERILOG"  and also specify the destination directory where you want to save your files

step 3: Click on the tab "translate" and check the results in verilog

Step 4 : verify results

Link for the coupons : Here

Click here to download Tool

Use password as : XHDL65@tech

Do write back to me if it was helpful
  

Please Note : Our course is now listed for Udemy training by Industry and leading companies use our courses  :
Analog Design- Intuitive Approach
Rc Circuits Analysis With LT Spice
Basics of Mosfet - Simplified View
Please use these links or share with someone who might be interested.
Note : Author discounts are already applied to these links.