There are two types of state machine(FSM)they are listed as:
1:Mealy machine
2:Moore machine
- Mealy machine: is a FSM whose output values are determined both by its current state and the current inputs.
- Moore machine: is a FSM whose output values are determined only by its current state only.
Example:
1)Mealy module: sequence detector
For the example go to the link below which is already available in our blog
httngp://verilog-code.blogspot.in/2014/08/finite-state-machine-design-for.html
2)Moore machine: traffic light controller
assumption made,
This module has input clock and output color of light .
output is assigned by the determining the state only, It consists of three states such as 00,01,10. it is shown in the example below.present state is set with respect to clock and output is set with respect to states hence output is not determined by input it is determined by the present state only.
//-------------------------------------------------------------------------------------------------------------------------//
module traffic_light( clk ,
light );
//--------------------------------------------------------------------------------------------------//
parameter RED =3'b000,GREEN=3'b010 ,YELLOW = 3'b001;
//-------------------------------------------------------------------------------- ------------------//
input clk ;
output [0:2]light ;
//---------------------------------------------------------------------------------------------------//
reg [0:1]state ;
reg [0:2]light ;
//-------------------------------------------------------------------------------------------------//
always@(posedge clk)
begin
case(state)
2'b00: begin
light<=YELLOW ;
state<=2'b01 ;
end
2'b01: begin
light<=GREEN ;
state<=2'b10 ;
end
2'b10: begin
light<=RED ;
state<=2'b00 ;
end
default:begin
light<=RED ;
state<=2'b00 ;
end
endcase
end
endmodule